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CCF Instruction
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ad5211d057
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23
src/cpu.rs
23
src/cpu.rs
@ -1031,10 +1031,17 @@ impl CPU {
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self.registers.set_flag(FlagRegister::Substract, true);
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self.registers.set_flag(FlagRegister::Substract, true);
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self.registers.set_flag(FlagRegister::HalfCarry, true);
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self.registers.set_flag(FlagRegister::HalfCarry, true);
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},
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},
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// Invert the carry flag
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Opcode::CCF => {
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self.registers.increment(Register::PC, 1);
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self.registers.set_flag(FlagRegister::Carry, !self.registers.get_flag(FlagRegister::Carry));
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self.registers.set_flag(FlagRegister::Substract, false);
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self.registers.set_flag(FlagRegister::HalfCarry, false);
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},
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// Disable interrupts
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// Disable interrupts
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Opcode::DI => {
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Opcode::DI => {
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bus.write(0xFFFF, 0x00); // Disable all interrupts
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self.registers.increment(Register::PC, 1);
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self.registers.increment(Register::PC, 1);
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bus.write(0xFFFF, 0x00); // Disable all interrupts
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},
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},
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Opcode::NOP => self.registers.increment(Register::PC, 1),
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Opcode::NOP => self.registers.increment(Register::PC, 1),
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// _ => println!("Illegal instruction"),
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// _ => println!("Illegal instruction"),
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@ -3005,6 +3012,20 @@ mod tests {
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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}
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}
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#[test]
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fn test_ccf_instructions() {
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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cpu.registers.set_flag(FlagRegister::Substract, true);
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cpu.registers.set_flag(FlagRegister::HalfCarry, true);
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cpu.registers.set_flag(FlagRegister::Carry, false);
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cpu.exec(Opcode::CCF, &mut bus);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
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}
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#[test]
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#[test]
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fn test_nop_instructions() {
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fn test_nop_instructions() {
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let mut cpu = CPU::new();
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let mut cpu = CPU::new();
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