From 09c9ef16aa621a5eed8ced8e0fa873e9c4f87f70 Mon Sep 17 00:00:00 2001 From: Franco Colmenarez Date: Wed, 20 Oct 2021 18:03:59 -0500 Subject: [PATCH] Refactor parameter bytes --- src/cpu.rs | 1087 ++++++++++++++++++++++++++-------------------------- 1 file changed, 548 insertions(+), 539 deletions(-) diff --git a/src/cpu.rs b/src/cpu.rs index 84ba728..b767738 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -219,6 +219,543 @@ pub enum OpcodeParameter { NoParam, } +#[derive(Debug, Copy, Clone)] +pub struct OpcodeParameterBytes(u8, u8, u8, u8); + +impl OpcodeParameterBytes { + + pub fn from_address(address: u16, bus: &Bus)-> OpcodeParameterBytes { + OpcodeParameterBytes( + bus.read(address), + bus.read(address + 1), + bus.read(address + 2), + bus.read(address + 3), + ) + } + + pub fn parse_opcode(&self) -> (Opcode, Cycles) { + let opcode = self.0; + let two_byte_param = join_bytes(self.2, self.1); + match opcode { + 0x06 => (Opcode::LD(OpcodeParameter::Register_U8(Register::B, self.1)), Cycles(1)), + 0x0E => (Opcode::LD(OpcodeParameter::Register_U8(Register::C, self.1)), Cycles(3)), + 0x16 => (Opcode::LD(OpcodeParameter::Register_U8(Register::D, self.1)), Cycles(2)), + 0x1E => (Opcode::LD(OpcodeParameter::Register_U8(Register::E, self.1)), Cycles(2)), + 0x26 => (Opcode::LD(OpcodeParameter::Register_U8(Register::H, self.1)), Cycles(2)), + 0x2E => (Opcode::LD(OpcodeParameter::Register_U8(Register::L, self.1)), Cycles(2)), + 0x7F => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), + 0x78 => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), + 0x79 => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), + 0x7A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), + 0x7B => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), + 0x7C => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), + 0x7D => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), + 0x7E => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), + 0x40 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::B)), Cycles(1)), + 0x41 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::C)), Cycles(1)), + 0x42 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::D)), Cycles(1)), + 0x43 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::E)), Cycles(1)), + 0x44 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::H)), Cycles(1)), + 0x45 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::L)), Cycles(1)), + 0x46 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::HL)), Cycles(2)), + 0x48 => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::B)), Cycles(1)), + 0x49 => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::C)), Cycles(1)), + 0x4A => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::D)), Cycles(1)), + 0x4B => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::E)), Cycles(1)), + 0x4C => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::H)), Cycles(1)), + 0x4D => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::L)), Cycles(1)), + 0x4E => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::HL)), Cycles(2)), + 0x50 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::B)), Cycles(1)), + 0x51 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::C)), Cycles(1)), + 0x52 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::D)), Cycles(1)), + 0x53 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::E)), Cycles(1)), + 0x54 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::H)), Cycles(1)), + 0x55 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::L)), Cycles(1)), + 0x56 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::HL)), Cycles(2)), + 0x58 => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::B)), Cycles(1)), + 0x59 => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::C)), Cycles(1)), + 0x5A => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::D)), Cycles(1)), + 0x5B => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::E)), Cycles(1)), + 0x5C => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::H)), Cycles(1)), + 0x5D => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::L)), Cycles(1)), + 0x5E => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::HL)), Cycles(2)), + 0x60 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::B)), Cycles(1)), + 0x61 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::C)), Cycles(1)), + 0x62 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::D)), Cycles(1)), + 0x63 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::E)), Cycles(1)), + 0x64 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::H)), Cycles(1)), + 0x65 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::L)), Cycles(1)), + 0x66 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::HL)), Cycles(2)), + 0x68 => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::B)), Cycles(1)), + 0x69 => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::C)), Cycles(1)), + 0x6A => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::D)), Cycles(1)), + 0x6B => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::E)), Cycles(1)), + 0x6C => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::H)), Cycles(1)), + 0x6D => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::L)), Cycles(1)), + 0x6E => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::HL)), Cycles(2)), + 0x70 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::B)), Cycles(2)), + 0x71 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::C)), Cycles(2)), + 0x72 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::D)), Cycles(2)), + 0x73 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::E)), Cycles(2)), + 0x74 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::H)), Cycles(2)), + 0x75 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::L)), Cycles(2)), + 0x47 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::A)), Cycles(1)), + 0x4F => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::A)), Cycles(1)), + 0x57 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::A)), Cycles(1)), + 0x5F => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::A)), Cycles(1)), + 0x67 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::A)), Cycles(1)), + 0x6F => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::A)), Cycles(1)), + 0x02 => (Opcode::LD(OpcodeParameter::Register_Register(Register::BC, Register::A)), Cycles(2)), + 0x12 => (Opcode::LD(OpcodeParameter::Register_Register(Register::DE, Register::A)), Cycles(2)), + 0x77 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::A)), Cycles(2)), + 0x36 => (Opcode::LD(OpcodeParameter::Register_U8(Register::HL, self.1)), Cycles(3)), + 0x0A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::BC)), Cycles(2)), + 0x1A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::DE)), Cycles(2)), + 0xFA => (Opcode::LD(OpcodeParameter::Register_U16(Register::A, two_byte_param)), Cycles(4)), + 0x3E => (Opcode::LD(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), + 0xEA => (Opcode::LD(OpcodeParameter::U16_Register(two_byte_param, Register::A)), Cycles(4)), + 0xF2 => (Opcode::LD(OpcodeParameter::Register_FF00plusRegister(Register::A, Register::C)), Cycles(2)), + 0xE2 => (Opcode::LD(OpcodeParameter::FF00plusRegister_Register(Register::C, Register::A)), Cycles(2)), + 0x3A => (Opcode::LDD(OpcodeParameter::Register_RegisterDecrement(Register::A, Register::HL)), Cycles(2)), + 0x32 => (Opcode::LDD(OpcodeParameter::RegisterDecrement_Register(Register::HL, Register::A)), Cycles(2)), + 0x2A => (Opcode::LDI(OpcodeParameter::Register_RegisterIncrement(Register::A, Register::HL)), Cycles(2)), + 0x22 => (Opcode::LDI(OpcodeParameter::RegisterIncrement_Register(Register::HL, Register::A)), Cycles(2)), + 0xE0 => (Opcode::LD(OpcodeParameter::FF00plusU8_Register(self.1, Register::A)), Cycles(3)), + 0xF0 => (Opcode::LD(OpcodeParameter::Register_FF00plusU8(Register::A, self.1)), Cycles(3)), + 0x01 => (Opcode::LD(OpcodeParameter::Register_U16(Register::BC, two_byte_param)), Cycles(3)), + 0x11 => (Opcode::LD(OpcodeParameter::Register_U16(Register::DE, two_byte_param)), Cycles(3)), + 0x21 => (Opcode::LD(OpcodeParameter::Register_U16(Register::HL, two_byte_param)), Cycles(3)), + 0x31 => (Opcode::LD(OpcodeParameter::Register_U16(Register::SP, two_byte_param)), Cycles(3)), + 0xF9 => (Opcode::LD(OpcodeParameter::Register_Register(Register::SP, Register::HL)), Cycles(2)), + 0xF8 => (Opcode::LD(OpcodeParameter::Register_RegisterPlusI8(Register::HL, Register::SP, self.1 as i8)), Cycles(3)), + 0x08 => (Opcode::LD(OpcodeParameter::U16_Register(two_byte_param, Register::SP)), Cycles(5)), + 0xC5 => (Opcode::PUSH(Register::BC), Cycles(4)), + 0xD5 => (Opcode::PUSH(Register::DE), Cycles(4)), + 0xE5 => (Opcode::PUSH(Register::HL), Cycles(4)), + 0xF5 => (Opcode::PUSH(Register::AF), Cycles(4)), + 0xC1 => (Opcode::POP(Register::BC), Cycles(3)), + 0xD1 => (Opcode::POP(Register::DE), Cycles(3)), + 0xE1 => (Opcode::POP(Register::HL), Cycles(3)), + 0xF1 => (Opcode::POP(Register::AF), Cycles(3)), + 0x87 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), + 0x80 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), + 0x81 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), + 0x82 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), + 0x83 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), + 0x84 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), + 0x85 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), + 0x86 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), + 0xC6 => (Opcode::ADD(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), + 0x09 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::BC)), Cycles(2)), + 0x19 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::DE)), Cycles(2)), + 0x29 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::HL)), Cycles(2)), + 0x39 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::SP)), Cycles(2)), + 0xE8 => (Opcode::ADD(OpcodeParameter::Register_I8(Register::SP, self.1 as i8)), Cycles(4)), + 0x8F => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), + 0x88 => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), + 0x89 => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), + 0x8A => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), + 0x8B => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), + 0x8C => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), + 0x8D => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), + 0x8E => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), + 0xCE => (Opcode::ADC(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), + 0x97 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), + 0x90 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), + 0x91 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), + 0x92 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), + 0x93 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), + 0x94 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), + 0x95 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), + 0x96 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), + 0xD6 => (Opcode::SUB(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), + 0x9F => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), + 0x98 => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), + 0x99 => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), + 0x9A => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), + 0x9B => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), + 0x9C => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), + 0x9D => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), + 0x9E => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), + 0xDE => (Opcode::SBC(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), + 0xA7 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), + 0xA0 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), + 0xA1 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), + 0xA2 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), + 0xA3 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), + 0xA4 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), + 0xA5 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), + 0xA6 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), + 0xE6 => (Opcode::AND(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), + 0xB7 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), + 0xB0 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), + 0xB1 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), + 0xB2 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), + 0xB3 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), + 0xB4 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), + 0xB5 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), + 0xB6 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), + 0xF6 => (Opcode::OR(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), + 0xAF => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), + 0xA8 => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), + 0xA9 => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), + 0xAA => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), + 0xAB => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), + 0xAC => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), + 0xAD => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), + 0xAE => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), + 0xEE => (Opcode::XOR(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), + 0xBF => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), + 0xB8 => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), + 0xB9 => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), + 0xBA => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), + 0xBB => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), + 0xBC => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), + 0xBD => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), + 0xBE => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), + 0xFE => (Opcode::CP(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), + 0x3C => (Opcode::INC(true, false, Register::A), Cycles(1)), + 0x04 => (Opcode::INC(true, false, Register::B), Cycles(1)), + 0x0C => (Opcode::INC(true, false, Register::C), Cycles(1)), + 0x14 => (Opcode::INC(true, false, Register::D), Cycles(1)), + 0x1C => (Opcode::INC(true, false, Register::E), Cycles(1)), + 0x24 => (Opcode::INC(true, false, Register::H), Cycles(1)), + 0x2C => (Opcode::INC(true, false, Register::L), Cycles(1)), + 0x34 => (Opcode::INC(true, true, Register::HL), Cycles(3)), + 0x03 => (Opcode::INC(false, false, Register::BC), Cycles(2)), + 0x13 => (Opcode::INC(false, false, Register::DE), Cycles(2)), + 0x23 => (Opcode::INC(false, false, Register::HL), Cycles(2)), + 0x33 => (Opcode::INC(false, false, Register::SP), Cycles(2)), + 0x3D => (Opcode::DEC(true, false, Register::A), Cycles(1)), + 0x05 => (Opcode::DEC(true, false, Register::B), Cycles(1)), + 0x0D => (Opcode::DEC(true, false, Register::C), Cycles(1)), + 0x15 => (Opcode::DEC(true, false, Register::D), Cycles(1)), + 0x1D => (Opcode::DEC(true, false, Register::E), Cycles(1)), + 0x25 => (Opcode::DEC(true, false, Register::H), Cycles(1)), + 0x2D => (Opcode::DEC(true, false, Register::L), Cycles(1)), + 0x35 => (Opcode::DEC(true, true, Register::HL), Cycles(3)), + 0x0B => (Opcode::DEC(false, false, Register::BC), Cycles(2)), + 0x1B => (Opcode::DEC(false, false, Register::DE), Cycles(2)), + 0x2B => (Opcode::DEC(false, false, Register::HL), Cycles(2)), + 0x3B => (Opcode::DEC(false, false, Register::SP), Cycles(2)), + 0x27 => (Opcode::DAA, Cycles(1)), + 0x2F => (Opcode::CPL, Cycles(1)), + 0x3F => (Opcode::CCF, Cycles(1)), + 0x37 => (Opcode::SCF, Cycles(1)), + 0x17 => (Opcode::RLA, Cycles(1)), + 0x07 => (Opcode::RLCA, Cycles(1)), + 0x0F => (Opcode::RRCA, Cycles(1)), + 0x1F => (Opcode::RRA, Cycles(1)), + 0xCB => match self.1 { + 0x00 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::B))), Cycles(2)), + 0x01 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::C))), Cycles(2)), + 0x02 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::D))), Cycles(2)), + 0x03 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::E))), Cycles(2)), + 0x04 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::H))), Cycles(2)), + 0x05 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::L))), Cycles(2)), + 0x06 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::HL))), Cycles(4)), + 0x07 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::A))), Cycles(2)), + + 0x08 => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::B))), Cycles(2)), + 0x09 => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::C))), Cycles(2)), + 0x0A => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::D))), Cycles(2)), + 0x0B => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::E))), Cycles(2)), + 0x0C => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::H))), Cycles(2)), + 0x0D => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::L))), Cycles(2)), + 0x0E => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::HL))), Cycles(4)), + 0x0F => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::A))), Cycles(2)), + + 0x10 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::B))), Cycles(2)), + 0x11 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::C))), Cycles(2)), + 0x12 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::D))), Cycles(2)), + 0x13 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::E))), Cycles(2)), + 0x14 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::H))), Cycles(2)), + 0x15 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::L))), Cycles(2)), + 0x16 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::HL))), Cycles(4)), + 0x17 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::A))), Cycles(2)), + + 0x18 => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::B))), Cycles(2)), + 0x19 => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::C))), Cycles(2)), + 0x1A => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::D))), Cycles(2)), + 0x1B => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::E))), Cycles(2)), + 0x1C => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::H))), Cycles(2)), + 0x1D => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::L))), Cycles(2)), + 0x1E => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::HL))), Cycles(2)), + 0x1F => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::A))), Cycles(2)), + + 0x20 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::B))), Cycles(2)), + 0x21 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::C))), Cycles(2)), + 0x22 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::D))), Cycles(2)), + 0x23 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::E))), Cycles(2)), + 0x24 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::H))), Cycles(2)), + 0x25 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::L))), Cycles(2)), + 0x26 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::HL))), Cycles(4)), + 0x27 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::A))), Cycles(2)), + + 0x28 => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::B))), Cycles(2)), + 0x29 => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::C))), Cycles(2)), + 0x2A => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::D))), Cycles(2)), + 0x2B => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::E))), Cycles(2)), + 0x2C => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::H))), Cycles(2)), + 0x2D => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::L))), Cycles(2)), + 0x2E => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::HL))), Cycles(4)), + 0x2F => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::A))), Cycles(2)), + + 0x30 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::B))), Cycles(2)), + 0x31 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::C))), Cycles(2)), + 0x32 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::D))), Cycles(2)), + 0x33 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::E))), Cycles(2)), + 0x34 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::H))), Cycles(2)), + 0x35 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::L))), Cycles(2)), + 0x36 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::HL))), Cycles(4)), + 0x37 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::A))), Cycles(2)), + + 0x38 => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::B))), Cycles(2)), + 0x39 => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::C))), Cycles(2)), + 0x3A => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::D))), Cycles(2)), + 0x3B => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::E))), Cycles(2)), + 0x3C => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::H))), Cycles(2)), + 0x3D => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::L))), Cycles(2)), + 0x3E => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::HL))), Cycles(4)), + 0x3F => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::A))), Cycles(2)), + + 0x40 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::B))), Cycles(2)), + 0x41 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::C))), Cycles(2)), + 0x42 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::D))), Cycles(2)), + 0x43 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::E))), Cycles(2)), + 0x44 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::H))), Cycles(2)), + 0x45 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::L))), Cycles(2)), + 0x46 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::HL))), Cycles(3)), + 0x47 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::A))), Cycles(2)), + 0x48 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::B))), Cycles(2)), + 0x49 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::C))), Cycles(2)), + 0x4A => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::D))), Cycles(2)), + 0x4B => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::E))), Cycles(2)), + 0x4C => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::H))), Cycles(2)), + 0x4D => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::L))), Cycles(2)), + 0x4E => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::HL))), Cycles(3)), + 0x4F => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::A))), Cycles(2)), + 0x50 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::B))), Cycles(2)), + 0x51 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::C))), Cycles(2)), + 0x52 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::D))), Cycles(2)), + 0x53 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::E))), Cycles(2)), + 0x54 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::H))), Cycles(2)), + 0x55 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::L))), Cycles(2)), + 0x56 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::HL))), Cycles(3)), + 0x57 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::A))), Cycles(2)), + 0x58 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::B))), Cycles(2)), + 0x59 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::C))), Cycles(2)), + 0x5A => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::D))), Cycles(2)), + 0x5B => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::E))), Cycles(2)), + 0x5C => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::H))), Cycles(2)), + 0x5D => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::L))), Cycles(2)), + 0x5E => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::HL))), Cycles(3)), + 0x5F => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::A))), Cycles(2)), + 0x60 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::B))), Cycles(2)), + 0x61 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::C))), Cycles(2)), + 0x62 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::D))), Cycles(2)), + 0x63 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::E))), Cycles(2)), + 0x64 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::H))), Cycles(2)), + 0x65 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::L))), Cycles(2)), + 0x66 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::HL))), Cycles(3)), + 0x67 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::A))), Cycles(2)), + 0x68 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::B))), Cycles(2)), + 0x69 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::C))), Cycles(2)), + 0x6A => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::D))), Cycles(2)), + 0x6B => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::E))), Cycles(2)), + 0x6C => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::H))), Cycles(2)), + 0x6D => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::L))), Cycles(2)), + 0x6E => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::HL))), Cycles(3)), + 0x6F => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::A))), Cycles(2)), + 0x70 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::B))), Cycles(2)), + 0x71 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::C))), Cycles(2)), + 0x72 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::D))), Cycles(2)), + 0x73 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::E))), Cycles(2)), + 0x74 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::H))), Cycles(2)), + 0x75 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::L))), Cycles(2)), + 0x76 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::HL))), Cycles(3)), + 0x77 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::A))), Cycles(2)), + 0x78 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::B))), Cycles(2)), + 0x79 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::C))), Cycles(2)), + 0x7A => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::D))), Cycles(2)), + 0x7B => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::E))), Cycles(2)), + 0x7C => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::H))), Cycles(2)), + 0x7D => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::L))), Cycles(2)), + 0x7E => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::HL))), Cycles(3)), + 0x7F => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::A))), Cycles(2)), + + 0x80 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::B))), Cycles(2)), + 0x81 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::C))), Cycles(2)), + 0x82 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::D))), Cycles(2)), + 0x83 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::E))), Cycles(2)), + 0x84 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::H))), Cycles(2)), + 0x85 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::L))), Cycles(2)), + 0x86 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::HL))), Cycles(4)), + 0x87 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::A))), Cycles(2)), + 0x88 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::B))), Cycles(2)), + 0x89 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::C))), Cycles(2)), + 0x8A => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::D))), Cycles(2)), + 0x8B => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::E))), Cycles(2)), + 0x8C => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::H))), Cycles(2)), + 0x8D => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::L))), Cycles(2)), + 0x8E => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::HL))), Cycles(4)), + 0x8F => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::A))), Cycles(2)), + 0x90 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::B))), Cycles(2)), + 0x91 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::C))), Cycles(2)), + 0x92 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::D))), Cycles(2)), + 0x93 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::E))), Cycles(2)), + 0x94 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::H))), Cycles(2)), + 0x95 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::L))), Cycles(2)), + 0x96 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::HL))), Cycles(4)), + 0x97 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::A))), Cycles(2)), + 0x98 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::B))), Cycles(2)), + 0x99 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::C))), Cycles(2)), + 0x9A => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::D))), Cycles(2)), + 0x9B => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::E))), Cycles(2)), + 0x9C => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::H))), Cycles(2)), + 0x9D => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::L))), Cycles(2)), + 0x9E => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::HL))), Cycles(4)), + 0x9F => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::A))), Cycles(2)), + 0xA0 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::B))), Cycles(2)), + 0xA1 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::C))), Cycles(2)), + 0xA2 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::D))), Cycles(2)), + 0xA3 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::E))), Cycles(2)), + 0xA4 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::H))), Cycles(2)), + 0xA5 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::L))), Cycles(2)), + 0xA6 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::HL))), Cycles(4)), + 0xA7 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::A))), Cycles(2)), + 0xA8 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::B))), Cycles(2)), + 0xA9 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::C))), Cycles(2)), + 0xAA => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::D))), Cycles(2)), + 0xAB => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::E))), Cycles(2)), + 0xAC => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::H))), Cycles(2)), + 0xAD => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::L))), Cycles(2)), + 0xAE => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::HL))), Cycles(4)), + 0xAF => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::A))), Cycles(2)), + 0xB0 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::B))), Cycles(2)), + 0xB1 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::C))), Cycles(2)), + 0xB2 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::D))), Cycles(2)), + 0xB3 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::E))), Cycles(2)), + 0xB4 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::H))), Cycles(2)), + 0xB5 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::L))), Cycles(2)), + 0xB6 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::HL))), Cycles(4)), + 0xB7 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::A))), Cycles(2)), + 0xB8 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::B))), Cycles(2)), + 0xB9 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::C))), Cycles(2)), + 0xBA => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::D))), Cycles(2)), + 0xBB => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::E))), Cycles(2)), + 0xBC => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::H))), Cycles(2)), + 0xBD => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::L))), Cycles(2)), + 0xBE => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::HL))), Cycles(4)), + 0xBF => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::A))), Cycles(2)), + + 0xC0 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::B))), Cycles(2)), + 0xC1 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::C))), Cycles(2)), + 0xC2 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::D))), Cycles(2)), + 0xC3 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::E))), Cycles(2)), + 0xC4 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::H))), Cycles(2)), + 0xC5 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::L))), Cycles(2)), + 0xC6 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::HL))), Cycles(4)), + 0xC7 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::A))), Cycles(2)), + 0xC8 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::B))), Cycles(2)), + 0xC9 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::C))), Cycles(2)), + 0xCA => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::D))), Cycles(2)), + 0xCB => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::E))), Cycles(2)), + 0xCC => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::H))), Cycles(2)), + 0xCD => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::L))), Cycles(2)), + 0xCE => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::HL))), Cycles(4)), + 0xCF => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::A))), Cycles(2)), + 0xD0 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::B))), Cycles(2)), + 0xD1 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::C))), Cycles(2)), + 0xD2 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::D))), Cycles(2)), + 0xD3 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::E))), Cycles(2)), + 0xD4 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::H))), Cycles(2)), + 0xD5 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::L))), Cycles(2)), + 0xD6 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::HL))), Cycles(4)), + 0xD7 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::A))), Cycles(2)), + 0xD8 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::B))), Cycles(2)), + 0xD9 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::C))), Cycles(2)), + 0xDA => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::D))), Cycles(2)), + 0xDB => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::E))), Cycles(2)), + 0xDC => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::H))), Cycles(2)), + 0xDD => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::L))), Cycles(2)), + 0xDE => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::HL))), Cycles(4)), + 0xDF => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::A))), Cycles(2)), + 0xE0 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::B))), Cycles(2)), + 0xE1 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::C))), Cycles(2)), + 0xE2 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::D))), Cycles(2)), + 0xE3 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::E))), Cycles(2)), + 0xE4 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::H))), Cycles(2)), + 0xE5 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::L))), Cycles(2)), + 0xE6 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::HL))), Cycles(4)), + 0xE7 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::A))), Cycles(2)), + 0xE8 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::B))), Cycles(2)), + 0xE9 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::C))), Cycles(2)), + 0xEA => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::D))), Cycles(2)), + 0xEB => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::E))), Cycles(2)), + 0xEC => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::H))), Cycles(2)), + 0xED => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::L))), Cycles(2)), + 0xEE => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::HL))), Cycles(4)), + 0xEF => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::A))), Cycles(2)), + 0xF0 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::B))), Cycles(2)), + 0xF1 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::C))), Cycles(2)), + 0xF2 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::D))), Cycles(2)), + 0xF3 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::E))), Cycles(2)), + 0xF4 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::H))), Cycles(2)), + 0xF5 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::L))), Cycles(2)), + 0xF6 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::HL))), Cycles(4)), + 0xF7 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::A))), Cycles(2)), + 0xF8 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::B))), Cycles(2)), + 0xF9 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::C))), Cycles(2)), + 0xFA => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::D))), Cycles(2)), + 0xFB => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::E))), Cycles(2)), + 0xFC => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::H))), Cycles(2)), + 0xFD => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::L))), Cycles(2)), + 0xFE => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::HL))), Cycles(4)), + 0xFF => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::A))), Cycles(2)), + + _ => (Opcode::IllegalInstruction, Cycles(2)), + }, + 0xC3 => (Opcode::JP(OpcodeParameter::U16(two_byte_param)), Cycles(4)), + 0xC2 => (Opcode::JP(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), + 0xCA => (Opcode::JP(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), + 0xD2 => (Opcode::JP(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), + 0xDA => (Opcode::JP(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), + 0xE9 => (Opcode::JP(OpcodeParameter::Register(Register::HL)), Cycles(1)), + 0x18 => (Opcode::JR(OpcodeParameter::I8(self.1 as i8)), Cycles(3)), + 0x20 => (Opcode::JR(OpcodeParameter::FlagRegisterReset_I8(FlagRegister::Zero, self.1 as i8)), Cycles(2)), + 0x28 => (Opcode::JR(OpcodeParameter::FlagRegisterSet_I8(FlagRegister::Zero, self.1 as i8)), Cycles(2)), + 0x30 => (Opcode::JR(OpcodeParameter::FlagRegisterReset_I8(FlagRegister::Carry, self.1 as i8)), Cycles(2)), + 0x38 => (Opcode::JR(OpcodeParameter::FlagRegisterSet_I8(FlagRegister::Carry, self.1 as i8)), Cycles(2)), + 0xCD => (Opcode::CALL(OpcodeParameter::U16(two_byte_param)), Cycles(6)), + 0xC4 => (Opcode::CALL(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), + 0xCC => (Opcode::CALL(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), + 0xD4 => (Opcode::CALL(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), + 0xDC => (Opcode::CALL(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), + 0xC7 => (Opcode::RST(0x00), Cycles(4)), + 0xCF => (Opcode::RST(0x08), Cycles(4)), + 0xD7 => (Opcode::RST(0x10), Cycles(4)), + 0xDF => (Opcode::RST(0x18), Cycles(4)), + 0xE7 => (Opcode::RST(0x20), Cycles(4)), + 0xEF => (Opcode::RST(0x28), Cycles(4)), + 0xF7 => (Opcode::RST(0x30), Cycles(4)), + 0xFF => (Opcode::RST(0x38), Cycles(4)), + 0xC9 => (Opcode::RET(OpcodeParameter::NoParam), Cycles(4)), + 0xC0 => (Opcode::RET(OpcodeParameter::FlagRegisterReset(FlagRegister::Zero)), Cycles(2)), + 0xC8 => (Opcode::RET(OpcodeParameter::FlagRegisterSet(FlagRegister::Zero)), Cycles(2)), + 0xD0 => (Opcode::RET(OpcodeParameter::FlagRegisterReset(FlagRegister::Carry)), Cycles(2)), + 0xD8 => (Opcode::RET(OpcodeParameter::FlagRegisterSet(FlagRegister::Carry)), Cycles(2)), + 0xD9 => (Opcode::RETI, Cycles(4)), + 0xF3 => (Opcode::DI, Cycles(1)), + 0xFB => (Opcode::EI, Cycles(1)), + 0x76 => (Opcode::HALT, Cycles(1)), + 0x10 => (Opcode::STOP, Cycles(1)), + 0x00 => (Opcode::NOP, Cycles(1)), + _ => (Opcode::IllegalInstruction, Cycles(1)), + } + } +} + #[derive(Debug)] pub enum Opcode { LD(OpcodeParameter), @@ -311,13 +848,8 @@ impl CPU { self.cycles } - pub fn run(&mut self, bus: &mut Bus) { - let program_counter = self.registers.get(Register::PC); - let parameter_bytes = CPU::read_parameter_bytes(program_counter, bus); - let (opcode, cycles) = CPU::parse_opcode(parameter_bytes); - self.increment_cycles(cycles); - // println!("Opcode: {:02X?} | PC: {:04X?} | Params: {:02X?}", opcode, self.registers.get(Register::PC), ¶meter_bytes); - /* println!("A: {:02X} F: {:02X} B: {:02X} C: {:02X} D: {:02X} E: {:02X} H: {:02X} L: {:02X} SP: {:04X} PC: 00:{:04X} ({:02X} {:02X} {:02X} {:02X})", + fn log(&self, parameter_bytes: OpcodeParameterBytes) { + println!("A: {:02X} F: {:02X} B: {:02X} C: {:02X} D: {:02X} E: {:02X} H: {:02X} L: {:02X} SP: {:04X} PC: 00:{:04X} ({:02X} {:02X} {:02X} {:02X})", self.registers.get(Register::A), self.registers.get(Register::F), self.registers.get(Register::B), @@ -332,7 +864,15 @@ impl CPU { parameter_bytes.1, parameter_bytes.2, parameter_bytes.3, - ); */ + ); + } + + pub fn run(&mut self, bus: &mut Bus) { + let program_counter = self.registers.get(Register::PC); + let parameter_bytes = OpcodeParameterBytes::from_address(program_counter, bus); + let (opcode, cycles) = parameter_bytes.parse_opcode(); + self.log(parameter_bytes); + self.increment_cycles(cycles); self.exec(opcode, bus); self.increment_exec_calls_count(); } @@ -1187,537 +1727,6 @@ impl CPU { _ => {panic!("Illegal instruction");}, }; } - - fn read_parameter_bytes(address: u16, bus: &Bus) -> (u8, u8, u8, u8) { - ( - bus.read(address), - bus.read(address + 1), - bus.read(address + 2), - bus.read(address + 3), - ) - } - - pub fn parse_opcode(params: (u8, u8, u8, u8)) -> (Opcode, Cycles) { - let opcode = params.0; - let two_byte_param = join_bytes(params.2, params.1); - match opcode { - 0x06 => (Opcode::LD(OpcodeParameter::Register_U8(Register::B, params.1)), Cycles(1)), - 0x0E => (Opcode::LD(OpcodeParameter::Register_U8(Register::C, params.1)), Cycles(3)), - 0x16 => (Opcode::LD(OpcodeParameter::Register_U8(Register::D, params.1)), Cycles(2)), - 0x1E => (Opcode::LD(OpcodeParameter::Register_U8(Register::E, params.1)), Cycles(2)), - 0x26 => (Opcode::LD(OpcodeParameter::Register_U8(Register::H, params.1)), Cycles(2)), - 0x2E => (Opcode::LD(OpcodeParameter::Register_U8(Register::L, params.1)), Cycles(2)), - 0x7F => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0x78 => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0x79 => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0x7A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0x7B => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0x7C => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0x7D => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0x7E => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0x40 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::B)), Cycles(1)), - 0x41 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::C)), Cycles(1)), - 0x42 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::D)), Cycles(1)), - 0x43 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::E)), Cycles(1)), - 0x44 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::H)), Cycles(1)), - 0x45 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::L)), Cycles(1)), - 0x46 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::HL)), Cycles(2)), - 0x48 => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::B)), Cycles(1)), - 0x49 => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::C)), Cycles(1)), - 0x4A => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::D)), Cycles(1)), - 0x4B => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::E)), Cycles(1)), - 0x4C => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::H)), Cycles(1)), - 0x4D => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::L)), Cycles(1)), - 0x4E => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::HL)), Cycles(2)), - 0x50 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::B)), Cycles(1)), - 0x51 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::C)), Cycles(1)), - 0x52 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::D)), Cycles(1)), - 0x53 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::E)), Cycles(1)), - 0x54 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::H)), Cycles(1)), - 0x55 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::L)), Cycles(1)), - 0x56 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::HL)), Cycles(2)), - 0x58 => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::B)), Cycles(1)), - 0x59 => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::C)), Cycles(1)), - 0x5A => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::D)), Cycles(1)), - 0x5B => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::E)), Cycles(1)), - 0x5C => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::H)), Cycles(1)), - 0x5D => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::L)), Cycles(1)), - 0x5E => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::HL)), Cycles(2)), - 0x60 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::B)), Cycles(1)), - 0x61 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::C)), Cycles(1)), - 0x62 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::D)), Cycles(1)), - 0x63 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::E)), Cycles(1)), - 0x64 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::H)), Cycles(1)), - 0x65 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::L)), Cycles(1)), - 0x66 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::HL)), Cycles(2)), - 0x68 => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::B)), Cycles(1)), - 0x69 => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::C)), Cycles(1)), - 0x6A => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::D)), Cycles(1)), - 0x6B => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::E)), Cycles(1)), - 0x6C => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::H)), Cycles(1)), - 0x6D => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::L)), Cycles(1)), - 0x6E => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::HL)), Cycles(2)), - 0x70 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::B)), Cycles(2)), - 0x71 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::C)), Cycles(2)), - 0x72 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::D)), Cycles(2)), - 0x73 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::E)), Cycles(2)), - 0x74 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::H)), Cycles(2)), - 0x75 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::L)), Cycles(2)), - 0x47 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::A)), Cycles(1)), - 0x4F => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::A)), Cycles(1)), - 0x57 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::A)), Cycles(1)), - 0x5F => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::A)), Cycles(1)), - 0x67 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::A)), Cycles(1)), - 0x6F => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::A)), Cycles(1)), - 0x02 => (Opcode::LD(OpcodeParameter::Register_Register(Register::BC, Register::A)), Cycles(2)), - 0x12 => (Opcode::LD(OpcodeParameter::Register_Register(Register::DE, Register::A)), Cycles(2)), - 0x77 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::A)), Cycles(2)), - 0x36 => (Opcode::LD(OpcodeParameter::Register_U8(Register::HL, params.1)), Cycles(3)), - 0x0A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::BC)), Cycles(2)), - 0x1A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::DE)), Cycles(2)), - 0xFA => (Opcode::LD(OpcodeParameter::Register_U16(Register::A, two_byte_param)), Cycles(4)), - 0x3E => (Opcode::LD(OpcodeParameter::Register_U8(Register::A, params.1)), Cycles(2)), - 0xEA => (Opcode::LD(OpcodeParameter::U16_Register(two_byte_param, Register::A)), Cycles(4)), - 0xF2 => (Opcode::LD(OpcodeParameter::Register_FF00plusRegister(Register::A, Register::C)), Cycles(2)), - 0xE2 => (Opcode::LD(OpcodeParameter::FF00plusRegister_Register(Register::C, Register::A)), Cycles(2)), - 0x3A => (Opcode::LDD(OpcodeParameter::Register_RegisterDecrement(Register::A, Register::HL)), Cycles(2)), - 0x32 => (Opcode::LDD(OpcodeParameter::RegisterDecrement_Register(Register::HL, Register::A)), Cycles(2)), - 0x2A => (Opcode::LDI(OpcodeParameter::Register_RegisterIncrement(Register::A, Register::HL)), Cycles(2)), - 0x22 => (Opcode::LDI(OpcodeParameter::RegisterIncrement_Register(Register::HL, Register::A)), Cycles(2)), - 0xE0 => (Opcode::LD(OpcodeParameter::FF00plusU8_Register(params.1, Register::A)), Cycles(3)), - 0xF0 => (Opcode::LD(OpcodeParameter::Register_FF00plusU8(Register::A, params.1)), Cycles(3)), - 0x01 => (Opcode::LD(OpcodeParameter::Register_U16(Register::BC, two_byte_param)), Cycles(3)), - 0x11 => (Opcode::LD(OpcodeParameter::Register_U16(Register::DE, two_byte_param)), Cycles(3)), - 0x21 => (Opcode::LD(OpcodeParameter::Register_U16(Register::HL, two_byte_param)), Cycles(3)), - 0x31 => (Opcode::LD(OpcodeParameter::Register_U16(Register::SP, two_byte_param)), Cycles(3)), - 0xF9 => (Opcode::LD(OpcodeParameter::Register_Register(Register::SP, Register::HL)), Cycles(2)), - 0xF8 => (Opcode::LD(OpcodeParameter::Register_RegisterPlusI8(Register::HL, Register::SP, params.1 as i8)), Cycles(3)), - 0x08 => (Opcode::LD(OpcodeParameter::U16_Register(two_byte_param, Register::SP)), Cycles(5)), - 0xC5 => (Opcode::PUSH(Register::BC), Cycles(4)), - 0xD5 => (Opcode::PUSH(Register::DE), Cycles(4)), - 0xE5 => (Opcode::PUSH(Register::HL), Cycles(4)), - 0xF5 => (Opcode::PUSH(Register::AF), Cycles(4)), - 0xC1 => (Opcode::POP(Register::BC), Cycles(3)), - 0xD1 => (Opcode::POP(Register::DE), Cycles(3)), - 0xE1 => (Opcode::POP(Register::HL), Cycles(3)), - 0xF1 => (Opcode::POP(Register::AF), Cycles(3)), - 0x87 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0x80 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0x81 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0x82 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0x83 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0x84 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0x85 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0x86 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xC6 => (Opcode::ADD(OpcodeParameter::Register_U8(Register::A, params.1)), Cycles(2)), - 0x09 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::BC)), Cycles(2)), - 0x19 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::DE)), Cycles(2)), - 0x29 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::HL)), Cycles(2)), - 0x39 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::SP)), Cycles(2)), - 0xE8 => (Opcode::ADD(OpcodeParameter::Register_I8(Register::SP, params.1 as i8)), Cycles(4)), - 0x8F => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0x88 => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0x89 => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0x8A => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0x8B => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0x8C => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0x8D => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0x8E => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xCE => (Opcode::ADC(OpcodeParameter::Register_U8(Register::A, params.1)), Cycles(2)), - 0x97 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0x90 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0x91 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0x92 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0x93 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0x94 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0x95 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0x96 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xD6 => (Opcode::SUB(OpcodeParameter::Register_U8(Register::A, params.1)), Cycles(2)), - 0x9F => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0x98 => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0x99 => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0x9A => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0x9B => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0x9C => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0x9D => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0x9E => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xDE => (Opcode::SBC(OpcodeParameter::Register_U8(Register::A, params.1)), Cycles(2)), - 0xA7 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0xA0 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0xA1 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0xA2 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0xA3 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0xA4 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0xA5 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0xA6 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xE6 => (Opcode::AND(OpcodeParameter::Register_U8(Register::A, params.1)), Cycles(2)), - 0xB7 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0xB0 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0xB1 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0xB2 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0xB3 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0xB4 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0xB5 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0xB6 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xF6 => (Opcode::OR(OpcodeParameter::Register_U8(Register::A, params.1)), Cycles(2)), - 0xAF => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0xA8 => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0xA9 => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0xAA => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0xAB => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0xAC => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0xAD => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0xAE => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xEE => (Opcode::XOR(OpcodeParameter::Register_U8(Register::A, params.1)), Cycles(2)), - 0xBF => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0xB8 => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0xB9 => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0xBA => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0xBB => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0xBC => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0xBD => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0xBE => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xFE => (Opcode::CP(OpcodeParameter::Register_U8(Register::A, params.1)), Cycles(2)), - 0x3C => (Opcode::INC(true, false, Register::A), Cycles(1)), - 0x04 => (Opcode::INC(true, false, Register::B), Cycles(1)), - 0x0C => (Opcode::INC(true, false, Register::C), Cycles(1)), - 0x14 => (Opcode::INC(true, false, Register::D), Cycles(1)), - 0x1C => (Opcode::INC(true, false, Register::E), Cycles(1)), - 0x24 => (Opcode::INC(true, false, Register::H), Cycles(1)), - 0x2C => (Opcode::INC(true, false, Register::L), Cycles(1)), - 0x34 => (Opcode::INC(true, true, Register::HL), Cycles(3)), - 0x03 => (Opcode::INC(false, false, Register::BC), Cycles(2)), - 0x13 => (Opcode::INC(false, false, Register::DE), Cycles(2)), - 0x23 => (Opcode::INC(false, false, Register::HL), Cycles(2)), - 0x33 => (Opcode::INC(false, false, Register::SP), Cycles(2)), - 0x3D => (Opcode::DEC(true, false, Register::A), Cycles(1)), - 0x05 => (Opcode::DEC(true, false, Register::B), Cycles(1)), - 0x0D => (Opcode::DEC(true, false, Register::C), Cycles(1)), - 0x15 => (Opcode::DEC(true, false, Register::D), Cycles(1)), - 0x1D => (Opcode::DEC(true, false, Register::E), Cycles(1)), - 0x25 => (Opcode::DEC(true, false, Register::H), Cycles(1)), - 0x2D => (Opcode::DEC(true, false, Register::L), Cycles(1)), - 0x35 => (Opcode::DEC(true, true, Register::HL), Cycles(3)), - 0x0B => (Opcode::DEC(false, false, Register::BC), Cycles(2)), - 0x1B => (Opcode::DEC(false, false, Register::DE), Cycles(2)), - 0x2B => (Opcode::DEC(false, false, Register::HL), Cycles(2)), - 0x3B => (Opcode::DEC(false, false, Register::SP), Cycles(2)), - 0x27 => (Opcode::DAA, Cycles(1)), - 0x2F => (Opcode::CPL, Cycles(1)), - 0x3F => (Opcode::CCF, Cycles(1)), - 0x37 => (Opcode::SCF, Cycles(1)), - 0x17 => (Opcode::RLA, Cycles(1)), - 0x07 => (Opcode::RLCA, Cycles(1)), - 0x0F => (Opcode::RRCA, Cycles(1)), - 0x1F => (Opcode::RRA, Cycles(1)), - 0xCB => match params.1 { - 0x00 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::B))), Cycles(2)), - 0x01 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::C))), Cycles(2)), - 0x02 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::D))), Cycles(2)), - 0x03 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::E))), Cycles(2)), - 0x04 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::H))), Cycles(2)), - 0x05 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::L))), Cycles(2)), - 0x06 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::HL))), Cycles(4)), - 0x07 => (Opcode::PrefixCB(Box::new(Opcode::RLC(Register::A))), Cycles(2)), - - 0x08 => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::B))), Cycles(2)), - 0x09 => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::C))), Cycles(2)), - 0x0A => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::D))), Cycles(2)), - 0x0B => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::E))), Cycles(2)), - 0x0C => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::H))), Cycles(2)), - 0x0D => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::L))), Cycles(2)), - 0x0E => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::HL))), Cycles(4)), - 0x0F => (Opcode::PrefixCB(Box::new(Opcode::RRC(Register::A))), Cycles(2)), - - 0x10 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::B))), Cycles(2)), - 0x11 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::C))), Cycles(2)), - 0x12 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::D))), Cycles(2)), - 0x13 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::E))), Cycles(2)), - 0x14 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::H))), Cycles(2)), - 0x15 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::L))), Cycles(2)), - 0x16 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::HL))), Cycles(4)), - 0x17 => (Opcode::PrefixCB(Box::new(Opcode::RL(Register::A))), Cycles(2)), - - 0x18 => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::B))), Cycles(2)), - 0x19 => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::C))), Cycles(2)), - 0x1A => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::D))), Cycles(2)), - 0x1B => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::E))), Cycles(2)), - 0x1C => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::H))), Cycles(2)), - 0x1D => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::L))), Cycles(2)), - 0x1E => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::HL))), Cycles(2)), - 0x1F => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::A))), Cycles(2)), - - 0x20 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::B))), Cycles(2)), - 0x21 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::C))), Cycles(2)), - 0x22 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::D))), Cycles(2)), - 0x23 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::E))), Cycles(2)), - 0x24 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::H))), Cycles(2)), - 0x25 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::L))), Cycles(2)), - 0x26 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::HL))), Cycles(4)), - 0x27 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::A))), Cycles(2)), - - 0x28 => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::B))), Cycles(2)), - 0x29 => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::C))), Cycles(2)), - 0x2A => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::D))), Cycles(2)), - 0x2B => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::E))), Cycles(2)), - 0x2C => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::H))), Cycles(2)), - 0x2D => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::L))), Cycles(2)), - 0x2E => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::HL))), Cycles(4)), - 0x2F => (Opcode::PrefixCB(Box::new(Opcode::SRA(Register::A))), Cycles(2)), - - 0x30 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::B))), Cycles(2)), - 0x31 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::C))), Cycles(2)), - 0x32 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::D))), Cycles(2)), - 0x33 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::E))), Cycles(2)), - 0x34 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::H))), Cycles(2)), - 0x35 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::L))), Cycles(2)), - 0x36 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::HL))), Cycles(4)), - 0x37 => (Opcode::PrefixCB(Box::new(Opcode::SWAP(Register::A))), Cycles(2)), - - 0x38 => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::B))), Cycles(2)), - 0x39 => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::C))), Cycles(2)), - 0x3A => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::D))), Cycles(2)), - 0x3B => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::E))), Cycles(2)), - 0x3C => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::H))), Cycles(2)), - 0x3D => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::L))), Cycles(2)), - 0x3E => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::HL))), Cycles(4)), - 0x3F => (Opcode::PrefixCB(Box::new(Opcode::SRL(Register::A))), Cycles(2)), - - 0x40 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::B))), Cycles(2)), - 0x41 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::C))), Cycles(2)), - 0x42 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::D))), Cycles(2)), - 0x43 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::E))), Cycles(2)), - 0x44 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::H))), Cycles(2)), - 0x45 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::L))), Cycles(2)), - 0x46 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::HL))), Cycles(3)), - 0x47 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I0, Register::A))), Cycles(2)), - 0x48 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::B))), Cycles(2)), - 0x49 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::C))), Cycles(2)), - 0x4A => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::D))), Cycles(2)), - 0x4B => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::E))), Cycles(2)), - 0x4C => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::H))), Cycles(2)), - 0x4D => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::L))), Cycles(2)), - 0x4E => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::HL))), Cycles(3)), - 0x4F => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I1, Register::A))), Cycles(2)), - 0x50 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::B))), Cycles(2)), - 0x51 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::C))), Cycles(2)), - 0x52 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::D))), Cycles(2)), - 0x53 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::E))), Cycles(2)), - 0x54 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::H))), Cycles(2)), - 0x55 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::L))), Cycles(2)), - 0x56 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::HL))), Cycles(3)), - 0x57 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I2, Register::A))), Cycles(2)), - 0x58 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::B))), Cycles(2)), - 0x59 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::C))), Cycles(2)), - 0x5A => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::D))), Cycles(2)), - 0x5B => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::E))), Cycles(2)), - 0x5C => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::H))), Cycles(2)), - 0x5D => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::L))), Cycles(2)), - 0x5E => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::HL))), Cycles(3)), - 0x5F => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I3, Register::A))), Cycles(2)), - 0x60 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::B))), Cycles(2)), - 0x61 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::C))), Cycles(2)), - 0x62 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::D))), Cycles(2)), - 0x63 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::E))), Cycles(2)), - 0x64 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::H))), Cycles(2)), - 0x65 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::L))), Cycles(2)), - 0x66 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::HL))), Cycles(3)), - 0x67 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::A))), Cycles(2)), - 0x68 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::B))), Cycles(2)), - 0x69 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::C))), Cycles(2)), - 0x6A => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::D))), Cycles(2)), - 0x6B => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::E))), Cycles(2)), - 0x6C => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::H))), Cycles(2)), - 0x6D => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::L))), Cycles(2)), - 0x6E => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::HL))), Cycles(3)), - 0x6F => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I5, Register::A))), Cycles(2)), - 0x70 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::B))), Cycles(2)), - 0x71 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::C))), Cycles(2)), - 0x72 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::D))), Cycles(2)), - 0x73 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::E))), Cycles(2)), - 0x74 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::H))), Cycles(2)), - 0x75 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::L))), Cycles(2)), - 0x76 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::HL))), Cycles(3)), - 0x77 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I6, Register::A))), Cycles(2)), - 0x78 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::B))), Cycles(2)), - 0x79 => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::C))), Cycles(2)), - 0x7A => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::D))), Cycles(2)), - 0x7B => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::E))), Cycles(2)), - 0x7C => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::H))), Cycles(2)), - 0x7D => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::L))), Cycles(2)), - 0x7E => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::HL))), Cycles(3)), - 0x7F => (Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I7, Register::A))), Cycles(2)), - - 0x80 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::B))), Cycles(2)), - 0x81 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::C))), Cycles(2)), - 0x82 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::D))), Cycles(2)), - 0x83 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::E))), Cycles(2)), - 0x84 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::H))), Cycles(2)), - 0x85 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::L))), Cycles(2)), - 0x86 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::HL))), Cycles(4)), - 0x87 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0, Register::A))), Cycles(2)), - 0x88 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::B))), Cycles(2)), - 0x89 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::C))), Cycles(2)), - 0x8A => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::D))), Cycles(2)), - 0x8B => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::E))), Cycles(2)), - 0x8C => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::H))), Cycles(2)), - 0x8D => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::L))), Cycles(2)), - 0x8E => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::HL))), Cycles(4)), - 0x8F => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I1, Register::A))), Cycles(2)), - 0x90 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::B))), Cycles(2)), - 0x91 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::C))), Cycles(2)), - 0x92 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::D))), Cycles(2)), - 0x93 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::E))), Cycles(2)), - 0x94 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::H))), Cycles(2)), - 0x95 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::L))), Cycles(2)), - 0x96 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::HL))), Cycles(4)), - 0x97 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::A))), Cycles(2)), - 0x98 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::B))), Cycles(2)), - 0x99 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::C))), Cycles(2)), - 0x9A => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::D))), Cycles(2)), - 0x9B => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::E))), Cycles(2)), - 0x9C => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::H))), Cycles(2)), - 0x9D => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::L))), Cycles(2)), - 0x9E => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::HL))), Cycles(4)), - 0x9F => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I3, Register::A))), Cycles(2)), - 0xA0 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::B))), Cycles(2)), - 0xA1 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::C))), Cycles(2)), - 0xA2 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::D))), Cycles(2)), - 0xA3 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::E))), Cycles(2)), - 0xA4 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::H))), Cycles(2)), - 0xA5 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::L))), Cycles(2)), - 0xA6 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::HL))), Cycles(4)), - 0xA7 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I4, Register::A))), Cycles(2)), - 0xA8 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::B))), Cycles(2)), - 0xA9 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::C))), Cycles(2)), - 0xAA => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::D))), Cycles(2)), - 0xAB => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::E))), Cycles(2)), - 0xAC => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::H))), Cycles(2)), - 0xAD => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::L))), Cycles(2)), - 0xAE => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::HL))), Cycles(4)), - 0xAF => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I5, Register::A))), Cycles(2)), - 0xB0 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::B))), Cycles(2)), - 0xB1 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::C))), Cycles(2)), - 0xB2 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::D))), Cycles(2)), - 0xB3 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::E))), Cycles(2)), - 0xB4 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::H))), Cycles(2)), - 0xB5 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::L))), Cycles(2)), - 0xB6 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::HL))), Cycles(4)), - 0xB7 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I6, Register::A))), Cycles(2)), - 0xB8 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::B))), Cycles(2)), - 0xB9 => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::C))), Cycles(2)), - 0xBA => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::D))), Cycles(2)), - 0xBB => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::E))), Cycles(2)), - 0xBC => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::H))), Cycles(2)), - 0xBD => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::L))), Cycles(2)), - 0xBE => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::HL))), Cycles(4)), - 0xBF => (Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I7, Register::A))), Cycles(2)), - - 0xC0 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::B))), Cycles(2)), - 0xC1 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::C))), Cycles(2)), - 0xC2 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::D))), Cycles(2)), - 0xC3 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::E))), Cycles(2)), - 0xC4 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::H))), Cycles(2)), - 0xC5 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::L))), Cycles(2)), - 0xC6 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::HL))), Cycles(4)), - 0xC7 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I0, Register::A))), Cycles(2)), - 0xC8 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::B))), Cycles(2)), - 0xC9 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::C))), Cycles(2)), - 0xCA => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::D))), Cycles(2)), - 0xCB => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::E))), Cycles(2)), - 0xCC => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::H))), Cycles(2)), - 0xCD => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::L))), Cycles(2)), - 0xCE => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::HL))), Cycles(4)), - 0xCF => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I1, Register::A))), Cycles(2)), - 0xD0 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::B))), Cycles(2)), - 0xD1 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::C))), Cycles(2)), - 0xD2 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::D))), Cycles(2)), - 0xD3 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::E))), Cycles(2)), - 0xD4 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::H))), Cycles(2)), - 0xD5 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::L))), Cycles(2)), - 0xD6 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::HL))), Cycles(4)), - 0xD7 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I2, Register::A))), Cycles(2)), - 0xD8 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::B))), Cycles(2)), - 0xD9 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::C))), Cycles(2)), - 0xDA => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::D))), Cycles(2)), - 0xDB => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::E))), Cycles(2)), - 0xDC => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::H))), Cycles(2)), - 0xDD => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::L))), Cycles(2)), - 0xDE => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::HL))), Cycles(4)), - 0xDF => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I3, Register::A))), Cycles(2)), - 0xE0 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::B))), Cycles(2)), - 0xE1 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::C))), Cycles(2)), - 0xE2 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::D))), Cycles(2)), - 0xE3 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::E))), Cycles(2)), - 0xE4 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::H))), Cycles(2)), - 0xE5 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::L))), Cycles(2)), - 0xE6 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::HL))), Cycles(4)), - 0xE7 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I4, Register::A))), Cycles(2)), - 0xE8 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::B))), Cycles(2)), - 0xE9 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::C))), Cycles(2)), - 0xEA => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::D))), Cycles(2)), - 0xEB => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::E))), Cycles(2)), - 0xEC => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::H))), Cycles(2)), - 0xED => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::L))), Cycles(2)), - 0xEE => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::HL))), Cycles(4)), - 0xEF => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I5, Register::A))), Cycles(2)), - 0xF0 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::B))), Cycles(2)), - 0xF1 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::C))), Cycles(2)), - 0xF2 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::D))), Cycles(2)), - 0xF3 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::E))), Cycles(2)), - 0xF4 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::H))), Cycles(2)), - 0xF5 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::L))), Cycles(2)), - 0xF6 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::HL))), Cycles(4)), - 0xF7 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I6, Register::A))), Cycles(2)), - 0xF8 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::B))), Cycles(2)), - 0xF9 => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::C))), Cycles(2)), - 0xFA => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::D))), Cycles(2)), - 0xFB => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::E))), Cycles(2)), - 0xFC => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::H))), Cycles(2)), - 0xFD => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::L))), Cycles(2)), - 0xFE => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::HL))), Cycles(4)), - 0xFF => (Opcode::PrefixCB(Box::new(Opcode::SET(BitIndex::I7, Register::A))), Cycles(2)), - - _ => (Opcode::IllegalInstruction, Cycles(2)), - }, - 0xC3 => (Opcode::JP(OpcodeParameter::U16(two_byte_param)), Cycles(4)), - 0xC2 => (Opcode::JP(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), - 0xCA => (Opcode::JP(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), - 0xD2 => (Opcode::JP(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), - 0xDA => (Opcode::JP(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), - 0xE9 => (Opcode::JP(OpcodeParameter::Register(Register::HL)), Cycles(1)), - 0x18 => (Opcode::JR(OpcodeParameter::I8(params.1 as i8)), Cycles(3)), - 0x20 => (Opcode::JR(OpcodeParameter::FlagRegisterReset_I8(FlagRegister::Zero, params.1 as i8)), Cycles(2)), - 0x28 => (Opcode::JR(OpcodeParameter::FlagRegisterSet_I8(FlagRegister::Zero, params.1 as i8)), Cycles(2)), - 0x30 => (Opcode::JR(OpcodeParameter::FlagRegisterReset_I8(FlagRegister::Carry, params.1 as i8)), Cycles(2)), - 0x38 => (Opcode::JR(OpcodeParameter::FlagRegisterSet_I8(FlagRegister::Carry, params.1 as i8)), Cycles(2)), - 0xCD => (Opcode::CALL(OpcodeParameter::U16(two_byte_param)), Cycles(6)), - 0xC4 => (Opcode::CALL(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), - 0xCC => (Opcode::CALL(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), - 0xD4 => (Opcode::CALL(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), - 0xDC => (Opcode::CALL(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), - 0xC7 => (Opcode::RST(0x00), Cycles(4)), - 0xCF => (Opcode::RST(0x08), Cycles(4)), - 0xD7 => (Opcode::RST(0x10), Cycles(4)), - 0xDF => (Opcode::RST(0x18), Cycles(4)), - 0xE7 => (Opcode::RST(0x20), Cycles(4)), - 0xEF => (Opcode::RST(0x28), Cycles(4)), - 0xF7 => (Opcode::RST(0x30), Cycles(4)), - 0xFF => (Opcode::RST(0x38), Cycles(4)), - 0xC9 => (Opcode::RET(OpcodeParameter::NoParam), Cycles(4)), - 0xC0 => (Opcode::RET(OpcodeParameter::FlagRegisterReset(FlagRegister::Zero)), Cycles(2)), - 0xC8 => (Opcode::RET(OpcodeParameter::FlagRegisterSet(FlagRegister::Zero)), Cycles(2)), - 0xD0 => (Opcode::RET(OpcodeParameter::FlagRegisterReset(FlagRegister::Carry)), Cycles(2)), - 0xD8 => (Opcode::RET(OpcodeParameter::FlagRegisterSet(FlagRegister::Carry)), Cycles(2)), - 0xD9 => (Opcode::RETI, Cycles(4)), - 0xF3 => (Opcode::DI, Cycles(1)), - 0xFB => (Opcode::EI, Cycles(1)), - 0x76 => (Opcode::HALT, Cycles(1)), - 0x10 => (Opcode::STOP, Cycles(1)), - 0x00 => (Opcode::NOP, Cycles(1)), - _ => (Opcode::IllegalInstruction, Cycles(1)), - } - } } #[cfg(test)]