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RET instructions
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parent
581e1c19d6
commit
199470cc70
50
src/cpu.rs
50
src/cpu.rs
@ -728,6 +728,16 @@ impl CPU {
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self.registers.increment(Register::PC, 1);
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match params {
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OpcodeParameter::NoParam => self.exec(Opcode::POP(Register::PC), bus),
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OpcodeParameter::FlagRegisterReset(flag) => {
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if !self.registers.get_flag(flag) {
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self.exec(Opcode::POP(Register::PC), bus);
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}
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},
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OpcodeParameter::FlagRegisterSet(flag) => {
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if self.registers.get_flag(flag) {
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self.exec(Opcode::POP(Register::PC), bus);
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}
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},
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_ => {},
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};
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},
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@ -1840,6 +1850,46 @@ mod tests {
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cpu.exec(Opcode::RET(OpcodeParameter::NoParam), &mut bus);
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assert_eq!(cpu.registers.get(Register::PC), 0x1234);
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assert_eq!(cpu.registers.get(Register::SP), sp + 2);
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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let sp = 0xD000;
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cpu.registers.set_flag(FlagRegister::Zero, false);
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cpu.registers.set(Register::SP, sp);
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bus.write_16bit(sp, 0x1234);
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cpu.exec(Opcode::RET(OpcodeParameter::FlagRegisterReset(FlagRegister::Zero)), &mut bus);
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assert_eq!(cpu.registers.get(Register::PC), 0x1234);
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assert_eq!(cpu.registers.get(Register::SP), sp + 2);
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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let sp = 0xD000;
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cpu.registers.set_flag(FlagRegister::Zero, true);
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cpu.registers.set(Register::SP, sp);
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bus.write_16bit(sp, 0x1234);
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cpu.exec(Opcode::RET(OpcodeParameter::FlagRegisterReset(FlagRegister::Zero)), &mut bus);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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assert_eq!(cpu.registers.get(Register::SP), sp);
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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let sp = 0xD000;
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cpu.registers.set_flag(FlagRegister::Zero, true);
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cpu.registers.set(Register::SP, sp);
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bus.write_16bit(sp, 0x1234);
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cpu.exec(Opcode::RET(OpcodeParameter::FlagRegisterSet(FlagRegister::Zero)), &mut bus);
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assert_eq!(cpu.registers.get(Register::PC), 0x1234);
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assert_eq!(cpu.registers.get(Register::SP), sp + 2);
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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let sp = 0xD000;
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cpu.registers.set_flag(FlagRegister::Zero, false);
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cpu.registers.set(Register::SP, sp);
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bus.write_16bit(sp, 0x1234);
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cpu.exec(Opcode::RET(OpcodeParameter::FlagRegisterSet(FlagRegister::Zero)), &mut bus);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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assert_eq!(cpu.registers.get(Register::SP), sp);
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}
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#[test]
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