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https://github.com/FranLMSP/rmg-001.git
synced 2024-11-23 10:12:11 +00:00
More MBC implementations
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70ac674fe9
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@ -364,6 +364,7 @@ impl PPU {
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}
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} else if self.lcd_y >= 144 && !self.get_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::VBlank)) {
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// Mode 1 Vertical blank
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self.window_y_counter = 0;
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self.set_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::VBlank), true);
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self.set_interrupt(Interrupt::VBlank, true);
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self.stat_interrupt();
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@ -380,7 +381,6 @@ impl PPU {
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// Frame completed
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if self.lcd_y > 153 {
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self.lcd_y = 0;
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self.window_y_counter = 0;
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}
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self.force_set_register(LCD_Y_ADDRESS, self.lcd_y);
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self.stat_interrupt();
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144
src/rom.rs
144
src/rom.rs
@ -65,6 +65,7 @@ pub fn load_rom(filename: &str) -> std::io::Result<Box<dyn ROM>> {
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MBC::MBC1 => Box::new(MBC1::new(data, info)),
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MBC::MBC2 => Box::new(MBC2::new(data, info)),
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MBC::MBC3 => Box::new(MBC3::new(data, info)),
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MBC::MBC5 => Box::new(MBC5::new(data, info)),
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_ => unimplemented!(),
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})
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}
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@ -194,6 +195,10 @@ impl ROMInfo {
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}
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}
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pub fn rom_size(&self) -> usize {
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0x4000 * self.rom_banks as usize
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}
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pub fn ram_size(&self) -> usize {
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0x2000 * self.ram_banks as usize
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}
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@ -240,6 +245,7 @@ pub struct MBC1 {
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rom_bank: u16,
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ram_bank: u8,
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ram_enable: bool,
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is_large_rom: bool,
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banking_mode: BankingMode,
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}
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@ -250,7 +256,8 @@ impl MBC1 {
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println!("Has RAM {}", info.has_ram);
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println!("ROM banks {}", info.rom_banks);
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println!("RAM banks {}", info.ram_banks);
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let ram = Vec::with_capacity(info.ram_size() as usize);
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let ram = vec![0; info.ram_size() as usize];
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let is_large_rom = info.rom_size() >= 1048576;
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Self {
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data,
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info,
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@ -258,33 +265,45 @@ impl MBC1 {
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rom_bank: 1,
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ram_bank: 0,
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ram_enable: false,
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is_large_rom,
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banking_mode: BankingMode::Simple,
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}
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}
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fn switch_rom_bank(&mut self, bank: u16) {
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self.rom_bank = bank;
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if (self.rom_bank & 0b11111) == 0 {
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self.rom_bank += 1;
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fn switch_rom_bank(&mut self, bank: u8) {
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self.rom_bank = bank as u16 & 0b11111;
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if self.rom_bank == 0 {
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self.rom_bank = 1;
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}
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if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
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self.rom_bank = self.info.rom_banks.saturating_sub(1);
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}
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//println!("switched to ROM bank {}", self.rom_bank);
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}
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fn switch_ram_bank(&mut self, bank: u8) {
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self.ram_bank = bank & 0b11;
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// println!("switched to RAM bank {}", self.ram_bank);
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}
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fn get_bank_zero_address(&self, address: u16) -> usize {
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if !self.is_large_rom {
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return address as usize;
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}
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match self.banking_mode {
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BankingMode::Simple => (address & 0x3FFF) as usize,
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BankingMode::Simple => address as usize,
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BankingMode::Advanced => {
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((self.ram_bank as usize) << 5) * ((address & 0x3FFF) as usize)
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// ((self.ram_bank as usize) << 19) | (address & 0x3FFF) as usize
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},
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}
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}
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fn get_bank_switchable_address(&self, address: u16) -> usize {
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let rom_bank = ((self.ram_bank as u16) << 5) | (self.rom_bank & 0b11111);
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((rom_bank as usize) << 14) | (address & 0x3FFF) as usize
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if self.is_large_rom {
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let rom_bank = ((self.ram_bank as u16) << 5) | (self.rom_bank & 0b11111);
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return ((rom_bank as usize) << 14) | (address & 0x3FFF) as usize;
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}
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return ((self.rom_bank as usize) << 14) | (address & 0x3FFF) as usize;
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}
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fn get_ram_address(&self, address: u16) -> usize {
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@ -309,7 +328,7 @@ impl ROM for MBC1 {
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None => 0xFF,
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};
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.info.has_ram && !self.ram_enable {
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if !self.info.has_ram || !self.ram_enable {
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return 0xFF;
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}
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return match self.ram.get(self.get_ram_address(address)) {
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@ -331,9 +350,9 @@ impl ROM for MBC1 {
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};
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return;
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} else if address >= 0x2000 && address <= 0x3FFF { // ROM bank number register
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self.switch_rom_bank(data as u16 & 0b00011111);
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self.switch_rom_bank(data);
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} else if address >= 0x4000 && address <= 0x5FFF { // ROM and RAM bank number register
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self.ram_bank = data & 0b11;
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self.switch_ram_bank(data);
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} else if address >= 0x6000 && address <= 0x7FFF { // Banking mode select
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self.banking_mode = match (data & 1) == 0 {
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true => BankingMode::Simple,
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@ -356,7 +375,6 @@ pub struct MBC2 {
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info: ROMInfo,
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ram: Vec<u8>,
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rom_bank: u16,
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ram_bank: u8,
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ram_enable: bool,
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}
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@ -367,19 +385,18 @@ impl MBC2 {
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println!("Has RAM {}", info.has_ram);
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println!("ROM banks {}", info.rom_banks);
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println!("RAM banks {}", info.ram_banks);
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let ram = Vec::with_capacity(info.ram_size() as usize);
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let ram = vec![0; 0x200];
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Self {
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data,
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info,
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ram,
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rom_bank: 1,
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ram_bank: 0,
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ram_enable: false,
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}
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}
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fn switch_rom_bank(&mut self, bank: u16) {
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self.rom_bank = bank;
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self.rom_bank = bank & 0b1111;
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if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
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self.rom_bank = self.info.rom_banks.saturating_sub(1);
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} else if self.rom_bank == 0 {
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@ -393,23 +410,22 @@ impl ROM for MBC2 {
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if BANK_ZERO.contains(&address) {
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return self.data[address as usize];
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} else if BANK_SWITCHABLE.contains(&address) {
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return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
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} else if address >= 0xA000 && address <= 0xA1FF {
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if !self.info.has_ram || !self.ram_enable {
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return self.data[((self.rom_bank as usize * 0x4000) + (address as usize % 0x4000)) as usize];
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} else if address >= 0xA000 {
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let address = (address as usize) & 0x1FF;
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if !self.ram_enable {
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return 0xFF;
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}
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return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
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return match self.ram.get(address as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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} else if address >= 0xA200 && address <= 0xBFFF {
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return self.read(0xA000 + (address % 0x0200));
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}
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return 0xFF;
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}
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fn write(&mut self, address: u16, data: u8) {
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if BANK_SWITCHABLE.contains(&address) {
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if BANK_ZERO.contains(&address) {
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if address.to_be_bytes()[0] & 1 == 0 {
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match data {
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0x0A => self.ram_enable = true,
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@ -418,6 +434,14 @@ impl ROM for MBC2 {
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} else {
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self.switch_rom_bank(data as u16);
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}
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} else if address >= 0xA000 {
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if !self.ram_enable {
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return;
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}
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let address = address & 0x1FF;
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if let Some(elem) = self.ram.get_mut(address as usize) {
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*elem = data;
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}
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}
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}
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}
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@ -438,7 +462,7 @@ impl MBC3 {
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println!("Has RAM {}", info.has_ram);
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println!("ROM banks {}", info.rom_banks);
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println!("RAM banks {}", info.ram_banks);
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let ram = Vec::with_capacity(info.ram_size() as usize);
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let ram = vec![0; info.ram_size() as usize];
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Self {
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data,
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info,
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@ -497,3 +521,75 @@ impl ROM for MBC3 {
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}
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}
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pub struct MBC5 {
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data: Vec<u8>,
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info: ROMInfo,
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ram: Vec<u8>,
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rom_bank: u16,
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ram_bank: u8,
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ram_enable: bool,
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}
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impl MBC5 {
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fn new(data: Vec<u8>, info: ROMInfo) -> Self {
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println!("MBC {:?}", info.mbc);
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println!("Region {:?}", info.region);
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println!("Has RAM {}", info.has_ram);
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println!("ROM banks {}", info.rom_banks);
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println!("RAM banks {}", info.ram_banks);
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let ram = vec![0; info.ram_size() as usize];
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Self {
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data,
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info,
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ram,
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rom_bank: 1,
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ram_bank: 0,
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ram_enable: false,
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}
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}
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}
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impl ROM for MBC5 {
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fn read(&self, address: u16) -> u8 {
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if BANK_ZERO.contains(&address) {
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return self.data[address as usize];
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} else if BANK_SWITCHABLE.contains(&address) {
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return match self.data.get(((self.rom_bank as usize * 0x4000) + (address as usize % 0x4000)) as usize) {
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Some(byte) => *byte,
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None => 0xFF,
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};
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.info.has_ram || !self.ram_enable {
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return 0xFF;
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}
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return match self.ram.get(((self.ram_bank as usize * 0x2000) + (address as usize % 0x2000)) as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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}
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return 0xFF;
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}
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fn write(&mut self, address: u16, data: u8) {
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if address <= 0x1FFF {
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match data & 0b1111 {
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0x0A => self.ram_enable = true,
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_ => self.ram_enable = false,
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};
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} else if address >= 0x2000 && address <= 0x2FFF {
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self.rom_bank = data as u16;
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} else if address >= 0x3000 && address <= 0x3FFF {
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self.rom_bank = ((data & 1) as u16) | (self.rom_bank & 0xF);
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} else if address >= 0x4000 && address <= 0x5FFF {
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self.ram_bank = data & 0b1111;
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.ram_enable || !self.info.has_ram {
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return;
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}
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if let Some(elem) = self.ram.get_mut(((self.ram_bank as usize * 0x2000) + (address as usize % 0x2000)) as usize) {
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*elem = data;
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}
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}
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}
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}
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