mirror of
https://github.com/FranLMSP/rmg-001.git
synced 2024-11-23 02:01:32 +00:00
Refactor MBCs
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parent
71692a05a5
commit
2ed5fdb823
@ -2,7 +2,7 @@ use std::ops::RangeInclusive;
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use crate::utils::{
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join_bytes
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};
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use crate::rom::ROM;
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use crate::rom::{ROM, load_rom};
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use crate::ppu::{
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PPU,
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DMA_ADDRESS,
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@ -27,7 +27,7 @@ pub const INTERRUPT_ENABLE_ADDRESS: u16 = 0xFFFF;
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pub const INTERRUPT_FLAG_ADDRESS: u16 = 0xFF0F;
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pub struct Bus {
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game_rom: ROM,
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game_rom: Box<dyn ROM>,
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data: [u8; 0x10000],
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pub ppu: PPU,
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pub joypad: Joypad,
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@ -41,7 +41,7 @@ impl Bus {
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println!("Please, specify a ROM file");
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std::process::exit(1);
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}
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let game_rom = match ROM::load_file(&args[1]) {
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let game_rom = match load_rom(&args[1]) {
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Ok(rom) => rom,
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Err(err) => {
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println!("Could not read ROM: {}", err);
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194
src/rom.rs
194
src/rom.rs
@ -14,10 +14,17 @@ pub const RAM_SIZE_ADDRESS: u16 = 0x0149;
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pub const ROM_SIZE_ADDRESS: u16 = 0x0148;
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pub const DESTINATION_CODE_ADDRESS: u16 = 0x014A;
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#[derive(Debug)]
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enum Region {
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Japanese,
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NonJapanese,
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pub fn load_rom(filename: &str) -> std::io::Result<Box<dyn ROM>> {
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let mut file = File::open(filename)?;
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let mut data = vec![];
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file.read_to_end(&mut data)?;
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let info = ROMInfo::from_bytes(&data);
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Ok(match info.mbc {
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MBC::NoMBC => Box::new(NoMBC::new(data, info)),
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MBC::MBC1 => Box::new(MBC1::new(data, info)),
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_ => unimplemented!(),
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})
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}
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#[derive(Debug, Copy, Clone)]
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@ -36,6 +43,12 @@ enum MBC {
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BandaiTIMA5,
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}
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#[derive(Debug)]
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enum Region {
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Japanese,
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NonJapanese,
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}
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#[derive(Debug)]
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enum BankingMode {
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Simple,
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@ -144,7 +157,41 @@ impl ROMInfo {
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}
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}
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pub struct ROM {
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pub trait ROM {
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fn read(&self, address: u16) -> u8;
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fn write(&mut self, address: u16, data: u8);
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}
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pub struct NoMBC {
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data: Vec<u8>,
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info: ROMInfo,
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}
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impl NoMBC {
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pub fn new(data: Vec<u8>, info: ROMInfo) -> Self {
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let rom = Self {
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data,
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info,
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};
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println!("MBC {:?}", rom.info.mbc);
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println!("Region {:?}", rom.info.region);
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rom
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}
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}
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impl ROM for NoMBC {
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fn read(&self, address: u16) -> u8 {
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match self.data.get(address as usize) {
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Some(byte) => *byte,
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None => 0xFF,
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}
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}
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fn write(&mut self, _address: u16, _data: u8) {}
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}
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pub struct MBC1 {
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data: Vec<u8>,
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info: ROMInfo,
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ram: Vec<u8>,
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@ -154,21 +201,15 @@ pub struct ROM {
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banking_mode: BankingMode,
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}
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impl ROM {
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pub fn load_file(filename: &str) -> std::io::Result<Self> {
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let mut file = File::open(filename)?;
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let mut data = vec![];
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file.read_to_end(&mut data)?;
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let info = ROMInfo::from_bytes(&data);
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impl MBC1 {
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fn new(data: Vec<u8>, info: ROMInfo) -> Self {
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println!("MBC {:?}", info.mbc);
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println!("Region {:?}", info.region);
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println!("Has RAM {}", info.has_ram);
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println!("ROM banks {}", info.rom_banks);
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println!("RAM banks {}", info.ram_banks);
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println!("Region {:?}", info.region);
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let ram = Vec::with_capacity(info.ram_size() as usize);
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Ok(Self {
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Self {
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data,
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info,
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ram,
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@ -176,78 +217,10 @@ impl ROM {
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ram_bank: 0,
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ram_enable: false,
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banking_mode: BankingMode::Simple,
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})
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}
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pub fn read(&self, address: u16) -> u8 {
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match self.info.mbc {
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MBC::NoMBC => {
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return match self.data.get(address as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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},
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MBC::MBC1 => {
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if BANK_ZERO.contains(&address) {
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return self.data[address as usize];
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} else if BANK_SWITCHABLE.contains(&address) {
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return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.info.has_ram {
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return 0xFF;
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}
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return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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}
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unreachable!("ROM read: Address {} not valid", address);
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},
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_ => unimplemented!(),
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}
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}
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pub fn write(&mut self, address: u16, data: u8) {
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match self.info.mbc {
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MBC::NoMBC => {},
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MBC::MBC1 => {
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if address <= 0x1FFF { // RAM enable register
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if !self.info.has_ram {
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return;
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}
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self.ram_enable = match data & 0x0F {
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0x0A => true,
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_ => false,
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};
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return;
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} else if address >= 0x2000 && address <= 0x3FFF { // ROM bank number register
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// println!("Switch bank to {:02X}", data);
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self.switch_rom_bank(data as u16 & 0b00011111);
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} else if address >= 0x4000 && address <= 0x5FFF { // ROM and RAM bank number register
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// println!("RAM bank {:02X}", data);
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self.ram_bank = data & 0b11;
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} else if address >= 0x6000 && address <= 0x7FFF { // Banking mode select
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self.banking_mode = match data & 1 {
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0 => BankingMode::Simple,
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1 => BankingMode::Advanced,
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_ => unreachable!(),
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}
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.ram_enable || !self.info.has_ram {
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return;
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}
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let address = address as usize - EXTERNAL_RAM.min().unwrap() as usize + (EXTERNAL_RAM.min().unwrap() as usize * self.ram_bank as usize);
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if let Some(elem) = self.ram.get_mut(address) {
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*elem = data;
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}
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self.switch_rom_bank(self.rom_bank + (data as u16 >> 5));
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}
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},
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_ => unimplemented!(),
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}
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}
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pub fn switch_rom_bank(&mut self, bank: u16) {
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fn switch_rom_bank(&mut self, bank: u16) {
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self.rom_bank = bank;
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if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
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self.rom_bank = self.info.rom_banks.saturating_sub(1);
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@ -257,3 +230,56 @@ impl ROM {
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}
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}
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}
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impl ROM for MBC1 {
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fn read(&self, address: u16) -> u8 {
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if BANK_ZERO.contains(&address) {
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return self.data[address as usize];
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} else if BANK_SWITCHABLE.contains(&address) {
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return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.info.has_ram {
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return 0xFF;
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}
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return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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}
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unreachable!("ROM read: Address {} not valid", address);
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}
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fn write(&mut self, address: u16, data: u8) {
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if address <= 0x1FFF { // RAM enable register
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if !self.info.has_ram {
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return;
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}
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self.ram_enable = match data & 0x0F {
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0x0A => true,
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_ => false,
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};
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return;
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} else if address >= 0x2000 && address <= 0x3FFF { // ROM bank number register
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// println!("Switch bank to {:02X}", data);
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self.switch_rom_bank(data as u16 & 0b00011111);
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} else if address >= 0x4000 && address <= 0x5FFF { // ROM and RAM bank number register
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// println!("RAM bank {:02X}", data);
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self.ram_bank = data & 0b11;
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} else if address >= 0x6000 && address <= 0x7FFF { // Banking mode select
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self.banking_mode = match data & 1 {
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0 => BankingMode::Simple,
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1 => BankingMode::Advanced,
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_ => unreachable!(),
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}
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.ram_enable || !self.info.has_ram {
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return;
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}
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let address = address as usize - EXTERNAL_RAM.min().unwrap() as usize + (EXTERNAL_RAM.min().unwrap() as usize * self.ram_bank as usize);
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if let Some(elem) = self.ram.get_mut(address) {
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*elem = data;
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}
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self.switch_rom_bank(self.rom_bank + (data as u16 >> 5));
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}
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}
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}
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