From 59acdd555e1586e6067d8b10cb28b4ae2a59f4b7 Mon Sep 17 00:00:00 2001
From: Franco Colmenarez <info@francoacg.com>
Date: Mon, 18 Oct 2021 12:03:24 -0500
Subject: [PATCH] Fix SRL instruction

---
 src/cpu.rs | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/src/cpu.rs b/src/cpu.rs
index 9d3d85d..77c1c53 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -811,6 +811,22 @@ impl CPU {
                         self.registers.set_flag(FlagRegister::Substract, false);
                         self.registers.set_flag(FlagRegister::HalfCarry, false);
                     },
+                    Opcode::SRL(register) => {
+                        let mut val = 0;
+                        match register.is_8bit() {
+                            true => val = self.registers.get_8bit(register),
+                            false => val = bus.read(self.registers.get(register)),
+                        };
+                        let val = val >> 1;
+                        match register.is_8bit() {
+                            true => self.registers.set(register, val as u16),
+                            false => bus.write(self.registers.get(register), val),
+                        };
+                        self.registers.set_flag(FlagRegister::Carry, get_bit(val, BitIndex::I0));
+                        self.registers.set_flag(FlagRegister::Zero, val == 0);
+                        self.registers.set_flag(FlagRegister::Substract, false);
+                        self.registers.set_flag(FlagRegister::HalfCarry, false);
+                    },
                     _ => {},
                 };
             },
@@ -2480,6 +2496,32 @@ mod tests {
         assert_eq!(cpu.registers.get(Register::PC), 0x102); */
     }
 
+    #[test]
+    fn test_prefix_cb_srl_instruction() {
+        let mut bus = Bus::new();
+        let mut cpu = CPU::new();
+        cpu.registers.set(Register::A, 0b00000010);
+        cpu.exec(Opcode::PrefixCB(Box::new(Opcode::SRL(Register::A))), &mut bus);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
+        assert_eq!(cpu.registers.get(Register::A), 0b00000001);
+        assert_eq!(cpu.registers.get(Register::PC), 0x102);
+
+        let mut cpu = CPU::new();
+        let addr = 0xC000;
+        bus.write(addr, 0b00000001);
+        cpu.registers.set(Register::HL, addr);
+        cpu.exec(Opcode::PrefixCB(Box::new(Opcode::SRL(Register::HL))), &mut bus);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
+        assert_eq!(bus.read(addr), 0b00000000);
+        assert_eq!(cpu.registers.get(Register::PC), 0x102);
+    }
+
     #[test]
     fn test_nop_instructions() {
         let mut cpu = CPU::new();