FranLMSP/rmg-001
1
0
Fork 0
mirror of https://github.com/FranLMSP/rmg-001.git synced 2024-11-23 10:12:11 +00:00
Code Issues Projects Releases Wiki Activity

Little tweak to timer

Browse Source
This commit is contained in:
Franco Colmenarez 2021-11-11 10:29:00 -05:00
parent c68f24ea05
commit 747a528c27
2 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/render.rs
View File

@ -39,6 +39,8 @@ pub fn start_eventloop() {
let mut emulator = Emulator::new(); let mut emulator = Emulator::new();
event_loop.run(move |event, _, control_flow| { event_loop.run(move |event, _, control_flow| {
*control_flow = ControlFlow::Wait;
// Handle input events // Handle input events
if input.update(&event) { if input.update(&event) {
// Close events // Close events

10
src/timer.rs
View File

@ -13,6 +13,8 @@ pub const TIMER_CONTROL_ADDRESS: u16 = 0xFF07;
pub struct Timer { pub struct Timer {
divider: u16, divider: u16,
prev_result: bool, prev_result: bool,
is_enabled: bool,
control: u8,
} }
impl Timer { impl Timer {
@ -20,7 +22,9 @@ impl Timer {
pub fn new() -> Self { pub fn new() -> Self {
Self { Self {
divider: 0, divider: 0,
control: 0,
prev_result: false, prev_result: false,
is_enabled: false,
} }
} }
@ -30,6 +34,8 @@ impl Timer {
} }
pub fn do_cycles(&mut self, bus: &mut Bus, cycles: Cycles) { pub fn do_cycles(&mut self, bus: &mut Bus, cycles: Cycles) {
self.is_enabled = Timer::is_timer_enabled(bus);
self.control = bus.read(TIMER_CONTROL_ADDRESS);
let mut count = 0; let mut count = 0;
while count < cycles.0 { while count < cycles.0 {
self.cycle(bus); self.cycle(bus);
@ -41,7 +47,7 @@ impl Timer {
fn cycle(&mut self, bus: &mut Bus) { fn cycle(&mut self, bus: &mut Bus) {
self.divider = self.divider.wrapping_add(1); self.divider = self.divider.wrapping_add(1);
let result = Timer::is_timer_enabled(bus) && self.get_tima_rate(bus); let result = self.is_enabled && self.get_tima_rate(bus);
if self.prev_result && !result { if self.prev_result && !result {
let tima = bus.read(TIMER_COUNTER_ADDRESS).wrapping_add(1); let tima = bus.read(TIMER_COUNTER_ADDRESS).wrapping_add(1);
@ -61,7 +67,7 @@ impl Timer {
} }
fn get_tima_rate(&self, bus: &Bus) -> bool { fn get_tima_rate(&self, bus: &Bus) -> bool {
let clock_select = bus.read(TIMER_CONTROL_ADDRESS) & 0b0000_0011; let clock_select = self.control & 0b0000_0011;
match clock_select { match clock_select {
0b00 => ((self.divider >> 9) & 1) == 1, 0b00 => ((self.divider >> 9) & 1) == 1,
0b01 => ((self.divider >> 3) & 1) == 1, 0b01 => ((self.divider >> 3) & 1) == 1,