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Fix cgb RAM

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This commit is contained in:
Franco Colmenarez 2021-12-27 14:10:39 -05:00
parent b4b560231e
commit 7925dd75c9
1 changed files with 3 additions and 3 deletions
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6
src/ram.rs
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@ -53,7 +53,7 @@ impl CGBRAM {
if self.bank > 7 { if self.bank > 7 {
self.bank = 7; self.bank = 7;
} else if bank == 0 { } else if bank == 0 {
self.bank = 0; self.bank = 1;
} }
} }
} }
@ -66,7 +66,7 @@ impl RAM for CGBRAM {
if address <= 0xCFFF { if address <= 0xCFFF {
return self.data[(address - 0xC000) as usize]; return self.data[(address - 0xC000) as usize];
} }
self.data[((address - 0xC000) as usize) * (self.bank as usize)] self.data[((address - 0xD000) as usize) + (4096 * (self.bank as usize))]
} }
fn write(&mut self, address: u16, value: u8) { fn write(&mut self, address: u16, value: u8) {
@ -75,6 +75,6 @@ impl RAM for CGBRAM {
} else if address <= 0xCFFF { } else if address <= 0xCFFF {
return self.data[(address - 0xC000) as usize] = value; return self.data[(address - 0xC000) as usize] = value;
} }
self.data[((address - 0xC000) as usize) * (self.bank as usize)] = value; self.data[((address - 0xD000) as usize) + (4096 * (self.bank as usize))] = value;
} }
} }