mirror of
https://github.com/FranLMSP/rmg-001.git
synced 2024-11-23 10:12:11 +00:00
Refactor timer
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parent
98be8f29dd
commit
806a4bf211
15
src/bus.rs
15
src/bus.rs
@ -54,14 +54,15 @@ pub const INTERRUPT_FLAG_ADDRESS: u16 = 0xFF0F;
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pub struct Bus {
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game_rom: ROM,
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data: [u8; 0x10000],
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pub reset_timer: bool,
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}
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impl Bus {
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pub fn new() -> Self {
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let game_rom = match ROM::load_file("ignore/dmg-acid2.gb".to_string()) {
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// let game_rom = match ROM::load_file("ignore/dr-mario.gb".to_string()) {
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// let game_rom = match ROM::load_file("roms/cpu_instrs.gb".to_string()) {
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// let game_rom = match ROM::load_file("roms/cpu_instrs_individual/01-special.gb".to_string()) {
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// let game_rom = match ROM::load_file("roms/cpu_instrs_individual/02-interrupts.gb".to_string()) {
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let game_rom = match ROM::load_file("roms/cpu_instrs_individual/02-interrupts.gb".to_string()) {
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// let game_rom = match ROM::load_file("roms/cpu_instrs_individual/03-op sp,hl.gb".to_string()) {
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// let game_rom = match ROM::load_file("roms/cpu_instrs_individual/04-op r,imm.gb".to_string()) {
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// let game_rom = match ROM::load_file("roms/cpu_instrs_individual/05-op rp.gb".to_string()) {
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@ -101,6 +102,7 @@ impl Bus {
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Self {
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data,
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game_rom,
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reset_timer: false,
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}
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}
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@ -120,6 +122,10 @@ impl Bus {
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// print!("{}", data as char);
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}
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if address == 0xFF06 {
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println!("Writing {:02X} to modulo", data);
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}
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if BANK_ZERO.in_range(address) || BANK_SWITCHABLE.in_range(address) {
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// println!("WRITING TO ROM");
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} else if WORK_RAM_1.in_range(address) || WORK_RAM_2.in_range(address) {
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@ -132,13 +138,14 @@ impl Bus {
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self.data[address as usize] = data;
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self.data[(WORK_RAM_1.begin() + (address - ECHO_RAM.begin())) as usize] = data; // Copy to the working RAM
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} else if address == TIMER_DIVIDER_REGISTER_ADDRESS {
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self.data[address as usize] = 0x00;
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println!("bus timer reset");
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self.reset_timer = true;
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} else if address == LCD_CONTROL_ADDRESS && get_bit(data, BitIndex::I7) {
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self.data[address as usize] = data;
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self.data[LCD_Y_ADDRESS as usize] = 0x00;
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} else if address == JOYPAD_ADDRESS {
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let byte = self.data[JOYPAD_ADDRESS as usize];
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self.data[JOYPAD_ADDRESS as usize] = (data & 0b00110000) | 0b11000000 | (byte & 0b00001111);
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self.data[JOYPAD_ADDRESS as usize] = (data & 0b11110000) | (byte & 0b00001111);
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} else {
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self.data[address as usize] = data;
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}
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17
src/cpu.rs
17
src/cpu.rs
@ -911,13 +911,16 @@ impl CPU {
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}
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pub fn handle_interrupt(&mut self, bus: &mut Bus, interrupt: Interrupt) {
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bus.set_interrupt_enable(interrupt, false);
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println!("Interrupt: {:?}", interrupt);
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bus.set_interrupt_flag(interrupt, false);
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let vector = interrupt.get_vector();
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self.exec(Opcode::CALL(OpcodeParameter::U16(vector)), bus);
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self.ime = false;
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self.exec(Opcode::CALL(OpcodeParameter::U16(interrupt.get_vector())), bus);
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}
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pub fn check_interrupts(&mut self, bus: &mut Bus) -> Option<Interrupt> {
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/* println!("IE {:08b}", bus.read(INTERRUPT_ENABLE_ADDRESS));
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println!("IF {:08b}", bus.read(INTERRUPT_FLAG_ADDRESS));
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println!("---"); */
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if !self.ime && !self.is_halted {
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return None;
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}
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@ -1809,9 +1812,11 @@ impl CPU {
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self.registers.increment(Register::PC, 2);
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},
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Opcode::NOP => self.registers.increment(Register::PC, 1),
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/* Opcode::IllegalInstruction => {panic!("Illegal instruction");},
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_ => {panic!("Illegal instruction");}, */
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_ => self.registers.increment(Register::PC, 1),
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Opcode::IllegalInstruction => {
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println!("Illegal instruction!");
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self.registers.increment(Register::PC, 1);
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},
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_ => unreachable!(),
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};
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}
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}
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@ -112,6 +112,10 @@ impl Emulator {
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self.cpu.reset_cycles();
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while self.cpu.get_cycles().0 <= cpu_cycles.0 {
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self.cpu.run(&mut self.bus);
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if self.bus.reset_timer {
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self.bus.reset_timer = false;
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self.timer.reset(&mut self.bus);
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}
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self.ppu.do_cycles(&mut self.bus, self.cpu.get_last_op_cycles());
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self.timer.do_cycles(&mut self.bus, self.cpu.get_last_op_cycles());
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}
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@ -73,8 +73,7 @@ impl Joypad {
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let direction = !get_bit(byte, BitIndex::I4);
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let action = !get_bit(byte, BitIndex::I5);
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let data = 0b11000000 |
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(byte & 0b00110000) |
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let data = (byte & 0b11110000) |
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(
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(!((direction && self.down) || (action && self.start)) as u8) << 3
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) | (
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23
src/ppu.rs
23
src/ppu.rs
@ -54,14 +54,14 @@ pub enum LCDControl {
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impl LCDControl {
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fn index(&self) -> BitIndex {
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match self {
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LCDControl::LCDEnable => BitIndex::I7,
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LCDControl::WindowTileMapAddress => BitIndex::I6,
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LCDControl::WindowEnable => BitIndex::I5,
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LCDControl::TileAddressMode => BitIndex::I4,
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LCDControl::BackgroundTileMapAddress => BitIndex::I3,
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LCDControl::ObjectSize => BitIndex::I2,
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LCDControl::ObjectEnable => BitIndex::I1,
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LCDControl::BackgroundPriority => BitIndex::I0,
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LCDControl::LCDEnable => BitIndex::I7,
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LCDControl::WindowTileMapAddress => BitIndex::I6,
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LCDControl::WindowEnable => BitIndex::I5,
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LCDControl::TileAddressMode => BitIndex::I4,
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LCDControl::BackgroundTileMapAddress => BitIndex::I3,
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LCDControl::ObjectSize => BitIndex::I2,
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LCDControl::ObjectEnable => BitIndex::I1,
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LCDControl::BackgroundPriority => BitIndex::I0,
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}
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}
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@ -174,7 +174,6 @@ impl PPU {
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fn check_lyc(bus: &mut Bus) {
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let lyc_compare = PPU::get_lcd_y(bus) == bus.read(LCD_Y_COMPARE_ADDRESS);
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if PPU::get_lcd_status(bus, LCDStatus::LYCInterrupt) && lyc_compare {
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println!("lyc");
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PPU::set_lcd_status(bus, LCDStatus::LYCFlag, lyc_compare);
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PPU::request_interrupt(bus, Interrupt::LCDSTAT);
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}
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@ -334,24 +333,22 @@ impl PPU {
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}
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fn get_palette(index: u8, palette_byte: u8) -> u8 {
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let index = index & 0b11;
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match index {
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0b00 => palette_byte & 0b11,
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0b01 => (palette_byte >> 2) & 0b11,
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0b10 => (palette_byte >> 4) & 0b11,
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0b11 => (palette_byte >> 6) & 0b11,
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_ => 0b00,
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_ => unreachable!(),
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}
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}
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fn get_pixel(two_bit_pixel: u8) -> Pixel {
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let two_bit_pixel = two_bit_pixel & 0b11;
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match two_bit_pixel {
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0b00 => Pixel::White,
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0b01 => Pixel::Light,
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0b10 => Pixel::Dark,
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0b11 => Pixel::Black,
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_ => Pixel::White,
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_ => unreachable!(),
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}
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}
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55
src/timer.rs
55
src/timer.rs
@ -11,23 +11,23 @@ pub const TIMER_MODULO_ADDRESS: u16 = 0xFF06;
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pub const TIMER_CONTROL_ADDRESS: u16 = 0xFF07;
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pub struct Timer {
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cycles: Cycles,
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divider: u16,
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prev_result: bool,
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}
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impl Timer {
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pub fn new() -> Self {
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Self {
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cycles: Cycles(0),
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divider: 0,
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prev_result: false,
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}
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}
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fn increment_cycles(&mut self, cycles: Cycles) {
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self.cycles.0 += cycles.0;
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}
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fn reset_cycles(&mut self) {
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self.cycles.0 = 0;
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pub fn reset(&mut self, bus: &mut Bus) {
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println!("timer reset");
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self.divider = 0;
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bus.force_write(TIMER_DIVIDER_REGISTER_ADDRESS, 0);
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}
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pub fn do_cycles(&mut self, bus: &mut Bus, cycles: Cycles) {
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@ -39,38 +39,37 @@ impl Timer {
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}
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fn cycle(&mut self, bus: &mut Bus) {
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let div = bus.read(TIMER_DIVIDER_REGISTER_ADDRESS);
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bus.write(TIMER_DIVIDER_REGISTER_ADDRESS, div.wrapping_add(1));
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self.divider = self.divider.wrapping_add(1);
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bus.force_write(TIMER_DIVIDER_REGISTER_ADDRESS, self.divider.to_be_bytes()[0]);
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if Timer::is_timer_enabled(bus) {
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let tima = bus.read(TIMER_COUNTER_ADDRESS);
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let tima_rate = Timer::get_tima_rate(bus);
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if self.cycles.0 >= tima_rate {
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if tima.checked_add(1) == None {
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bus.write(TIMER_COUNTER_ADDRESS, bus.read(TIMER_MODULO_ADDRESS));
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bus.set_interrupt_flag(Interrupt::Timer, true);
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} else {
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bus.write(TIMER_COUNTER_ADDRESS, tima.wrapping_add(1));
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}
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self.reset_cycles();
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let result = Timer::is_timer_enabled(bus) && self.get_tima_rate(bus);
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if self.prev_result && !result {
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let tima = bus.read(TIMER_COUNTER_ADDRESS).wrapping_add(1);
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if tima == 0 {
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bus.write(TIMER_COUNTER_ADDRESS, bus.read(TIMER_MODULO_ADDRESS));
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bus.set_interrupt_flag(Interrupt::Timer, true);
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println!("Timer interrupt set");
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} else {
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bus.write(TIMER_COUNTER_ADDRESS, tima);
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}
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}
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self.increment_cycles(Cycles(1));
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self.prev_result = result;
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}
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fn is_timer_enabled(bus: &Bus) -> bool {
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get_bit(bus.read(TIMER_CONTROL_ADDRESS), BitIndex::I2)
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}
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fn get_tima_rate(bus: &Bus) -> usize {
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fn get_tima_rate(&self, bus: &Bus) -> bool {
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let clock_select = bus.read(TIMER_CONTROL_ADDRESS) & 0b0000_0011;
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match clock_select {
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0b00 => 16,
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0b01 => 64,
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0b10 => 256,
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0b11 => 1024,
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_ => 1,
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0b00 => ((self.divider >> 9) & 1) == 1,
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0b01 => ((self.divider >> 3) & 1) == 1,
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0b10 => ((self.divider >> 5) & 1) == 1,
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0b11 => ((self.divider >> 7) & 1) == 1,
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_ => unreachable!(),
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}
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}
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}
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