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POP and RET instructions

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This commit is contained in:
Franco Colmenarez 2021-10-15 15:08:26 -05:00
parent 0a1edfa39e
commit 891a72ad73
1 changed files with 36 additions and 0 deletions
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36
src/cpu.rs
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@ -364,6 +364,22 @@ impl CPU {
}, },
// RST, same as Call // RST, same as Call
Opcode::RST(address) => self.exec(Opcode::CALL(OpcodeParameter::U16(address as u16)), bus), Opcode::RST(address) => self.exec(Opcode::CALL(OpcodeParameter::U16(address as u16)), bus),
// POP
Opcode::POP(register) => {
if register.is_16bit() {
let sp = self.registers.get(Register::SP);
let val = join_bytes(bus.read(sp + 1), bus.read(sp));
self.registers.set(register, val);
self.registers.increment(Register::SP, 2);
}
},
// RET, same as POP PC when no parameter is specified
Opcode::RET(params) => {
match params {
OpcodeParameter::NoParam => self.exec(Opcode::POP(Register::PC), bus),
_ => {},
}
}
// Rotate A Left // Rotate A Left
Opcode::RLCA => { Opcode::RLCA => {
let val = self.registers.get(Register::A).to_be_bytes()[1]; let val = self.registers.get(Register::A).to_be_bytes()[1];
@ -803,6 +819,26 @@ mod tests {
assert_eq!(cpu.registers.get(Register::SP), sp - 2); assert_eq!(cpu.registers.get(Register::SP), sp - 2);
assert_eq!(cpu.registers.get(Register::PC), 0x00F0); assert_eq!(cpu.registers.get(Register::PC), 0x00F0);
// POP
let mut cpu = CPU::new();
let sp = 0xFFDF;
cpu.registers.set(Register::SP, sp);
bus.write(sp, 0x34);
bus.write(sp + 1, 0x12);
cpu.exec(Opcode::POP(Register::HL), &mut bus);
assert_eq!(cpu.registers.get(Register::HL), 0x1234);
assert_eq!(cpu.registers.get(Register::SP), sp + 2);
// RET
let mut cpu = CPU::new();
let sp = 0xFFDF;
cpu.registers.set(Register::SP, sp);
bus.write(sp, 0x34);
bus.write(sp + 1, 0x12);
cpu.exec(Opcode::RET(OpcodeParameter::NoParam), &mut bus);
assert_eq!(cpu.registers.get(Register::PC), 0x1234);
assert_eq!(cpu.registers.get(Register::SP), sp + 2);
// INC // INC
let mut cpu = CPU::new(); let mut cpu = CPU::new();
cpu.registers.set(Register::A, 0); cpu.registers.set(Register::A, 0);