From 8b287c17c75683855c6726718632aaca20002bed Mon Sep 17 00:00:00 2001
From: Franco Colmenarez <info@francoacg.com>
Date: Tue, 19 Oct 2021 13:59:53 -0500
Subject: [PATCH] Fix ADD carry

---
 src/bus.rs     |  3 ++-
 src/console.rs |  1 +
 src/cpu.rs     | 15 ++++++++++++++-
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/bus.rs b/src/bus.rs
index bd8231a..2f70887 100644
--- a/src/bus.rs
+++ b/src/bus.rs
@@ -43,12 +43,13 @@ pub struct Bus {
 
 impl Bus {
     pub fn new() -> Self {
+        // let game_rom = match ROM::load_file("roms/cpu_instrs_individual/01-special.gb".to_string()) {
         let game_rom = match ROM::load_file("roms/cpu_instrs_individual/03-op sp,hl.gb".to_string()) {
             Ok(rom) => rom,
             _ => ROM::from_bytes(&[0; 0xFFFF])
         };
         Self {
-            data: [0xFF; 0x10000],
+            data: [0x00; 0x10000],
             game_rom,
         }
     }
diff --git a/src/console.rs b/src/console.rs
index 10c44b9..b6d9527 100644
--- a/src/console.rs
+++ b/src/console.rs
@@ -25,6 +25,7 @@ impl Console {
             self.cpu.run(&mut self.bus);
 
             // thread::sleep(time::Duration::from_millis(100));
+            // exit = self.cpu.get_exec_calls_count() >= 1258895;
             exit = self.cpu.get_exec_calls_count() >= 1068422;
         }
     }
diff --git a/src/cpu.rs b/src/cpu.rs
index 8bce3e7..3dcb59f 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -533,20 +533,25 @@ impl CPU {
                 match params {
                     OpcodeParameter::Register_Register(reg1, reg2) => {
                         if reg1.is_8bit() && reg2.is_8bit() {
+                            let res = (self.registers.get(reg2) as usize) + (self.registers.get(reg2) as usize);
                             self.registers.set_flag(FlagRegister::HalfCarry, add_half_carry(self.registers.get_8bit(reg1), self.registers.get_8bit(reg2)));
                             self.registers.increment(reg1, self.registers.get(reg2));
                             self.registers.set_flag(FlagRegister::Zero, self.registers.get(reg1) == 0);
+                            self.registers.set_flag(FlagRegister::Carry, res > 0xFF);
                         } else if reg1.is_16bit() && reg2.is_16bit() {
+                            let res = (self.registers.get(reg1) as usize) + (self.registers.get(reg2) as usize);
                             self.registers.set_flag(FlagRegister::HalfCarry, add_half_carry_16bit(self.registers.get(reg1), self.registers.get(reg2)));
                             self.registers.increment(reg1, self.registers.get(reg2));
+                            self.registers.set_flag(FlagRegister::Carry, res > 0xFFFF);
                         } else if reg1.is_8bit() && reg2.is_16bit() {
                             let val1 = self.registers.get(reg1);
                             let val2 = bus.read(self.registers.get(reg2)) as u16;
                             self.registers.increment(reg1, val2);
                             self.registers.set_flag(FlagRegister::HalfCarry, add_half_carry(val1.to_be_bytes()[1], val2.to_be_bytes()[1]));
                             self.registers.set_flag(FlagRegister::Zero, self.registers.get(reg1) == 0);
+                            self.registers.set_flag(FlagRegister::Carry, self.registers.get(reg1) == 0);
+                            self.registers.set_flag(FlagRegister::Carry, (val1 as usize + val2 as usize) > 0xFF);
                         }
-                        self.registers.set_flag(FlagRegister::Carry, self.registers.get(reg1) == 0);
                     },
                     OpcodeParameter::Register_U8(reg1, val) => {
                         self.registers.increment(Register::PC, 1);
@@ -2443,6 +2448,14 @@ mod tests {
         assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
         assert_eq!(cpu.registers.get(Register::BC), 0b0001000000000000);
         assert_eq!(cpu.registers.get(Register::PC), 0x101);
+
+        let mut cpu = CPU::new();
+        cpu.registers.set(Register::HL, 0x0000);
+        cpu.registers.set(Register::SP, 0x8000);
+        cpu.exec(Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::SP)), &mut bus);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
+        assert_eq!(cpu.registers.get(Register::HL), 0x8000);
+        assert_eq!(cpu.registers.get(Register::PC), 0x101);
     }
 
     #[test]