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16bit substraction is not really needed
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parent
7c804029ad
commit
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68
src/cpu.rs
68
src/cpu.rs
@ -563,59 +563,38 @@ impl CPU {
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},
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Opcode::SUB(params) => {
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self.registers.increment(Register::PC, 1);
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self.registers.set_flag(FlagRegister::Substract, true);
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let mut register = Register::A;
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let mut val1: u16 = 0;
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let mut val2: u16 = 0;
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match params {
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OpcodeParameter::Register_Register(reg1, reg2) => {
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register = reg1;
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val1 = self.registers.get(reg1);
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if reg1.is_8bit() && reg2.is_8bit() {
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let carry = self.registers.get(reg2) > self.registers.get(reg1);
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self.registers.set_flag(FlagRegister::Carry, carry);
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self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(self.registers.get_8bit(reg1), self.registers.get_8bit(reg2)));
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let mut val1 = self.registers.get(reg1);
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let val2 = self.registers.get(reg2);
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if carry {
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val1 = val1 | 0x100;
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}
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self.registers.set(reg1, val1 - val2);
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} else if reg1.is_16bit() && reg2.is_16bit() {
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let mut val1 = self.registers.get(reg1) as u32;
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let val2 = self.registers.get(reg2) as u32;
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let carry = val2 > val1;
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if carry {
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val1 = val1 | 0x10000;
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}
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let result = val1 - val2;
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self.registers.set(reg1, join_bytes(result.to_be_bytes()[2], result.to_be_bytes()[3]));
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self.registers.set_flag(FlagRegister::Carry, carry);
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self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(val1.to_be_bytes()[2], val2.to_be_bytes()[2]));
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val2 = self.registers.get(reg2);
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} else if reg1.is_8bit() && reg2.is_16bit() {
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let mut val1 = self.registers.get(reg1) as u16;
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let val2 = bus.read(self.registers.get(reg2)) as u16;
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let carry = val2 > val1;
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if carry {
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val1 = val1 | 0x100;
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val2 = bus.read(self.registers.get(reg2)) as u16;
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}
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self.registers.set(reg1, val1 - val2);
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self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(val1.to_be_bytes()[1], val2.to_be_bytes()[1]));
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self.registers.set_flag(FlagRegister::Carry, carry);
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}
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self.registers.set_flag(FlagRegister::Zero, self.registers.get(reg1) == 0);
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},
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OpcodeParameter::Register_U8(reg1, val) => {
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self.registers.increment(Register::PC, 1);
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let mut val1 = self.registers.get(reg1) as u16;
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let val2 = val as u16;
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register = reg1;
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val1 = self.registers.get(reg1);
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val2 = val as u16;
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},
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_ => {},
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};
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let carry = val2 > val1;
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if carry {
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val1 = val1 | 0x100;
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}
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let result = val1 - val2;
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self.registers.set(reg1, join_bytes(result.to_be_bytes()[0], result.to_be_bytes()[1]));
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self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(val1.to_be_bytes()[1], val2.to_be_bytes()[1]));
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self.registers.set_flag(FlagRegister::Zero, self.registers.get(reg1) == 0);
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println!("{} {}", val1, val2);
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self.registers.set(register, result);
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self.registers.set_flag(FlagRegister::Zero, self.registers.get(register) == 0);
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self.registers.set_flag(FlagRegister::Substract, true);
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self.registers.set_flag(FlagRegister::Carry, carry);
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},
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_ => {},
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};
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self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(val1.to_be_bytes()[1], val2.to_be_bytes()[1]));
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},
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// Increment by 1
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Opcode::INC(affect_flags, register) => {
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@ -2133,17 +2112,6 @@ mod tests {
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
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assert_eq!(cpu.registers.get(Register::B), 0);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::BC, 0b0001000000000000);
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cpu.registers.set(Register::HL, 0b0100100000000000);
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cpu.exec(Opcode::SUB(OpcodeParameter::Register_Register(Register::BC, Register::HL)), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
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assert_eq!(cpu.registers.get(Register::BC), 0b1100100000000000);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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}
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#[test]
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