diff --git a/src/cpu.rs b/src/cpu.rs
index 4d524d7..9d3d85d 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -779,6 +779,38 @@ impl CPU {
                         self.registers.set_flag(FlagRegister::Substract, false);
                         self.registers.set_flag(FlagRegister::HalfCarry, false);
                     },
+                    Opcode::SLA(register) => {
+                        let mut val = 0;
+                        match register.is_8bit() {
+                            true => val = self.registers.get_8bit(register) as i8,
+                            false => val = bus.read(self.registers.get(register)) as i8,
+                        };
+                        let val = val << 7;
+                        match register.is_8bit() {
+                            true => self.registers.set(register, val as u16),
+                            false => bus.write(self.registers.get(register), val as u8),
+                        };
+                        self.registers.set_flag(FlagRegister::Carry, get_bit(val as u8, BitIndex::I7));
+                        self.registers.set_flag(FlagRegister::Zero, val == 0);
+                        self.registers.set_flag(FlagRegister::Substract, false);
+                        self.registers.set_flag(FlagRegister::HalfCarry, false);
+                    },
+                    Opcode::SRA(register) => {
+                        let mut val = 0;
+                        match register.is_8bit() {
+                            true => val = self.registers.get_8bit(register) as i8,
+                            false => val = bus.read(self.registers.get(register)) as i8,
+                        };
+                        let val = val >> 7;
+                        match register.is_8bit() {
+                            true => self.registers.set(register, val as u16),
+                            false => bus.write(self.registers.get(register), val as u8),
+                        };
+                        self.registers.set_flag(FlagRegister::Carry, get_bit(val as u8, BitIndex::I0));
+                        self.registers.set_flag(FlagRegister::Zero, val == 0);
+                        self.registers.set_flag(FlagRegister::Substract, false);
+                        self.registers.set_flag(FlagRegister::HalfCarry, false);
+                    },
                     _ => {},
                 };
             },
@@ -2391,6 +2423,63 @@ mod tests {
         assert_eq!(cpu.registers.get(Register::PC), 0x102);
     }
 
+    #[test]
+    fn test_prefix_cb_sla_instruction() {
+        /* let mut bus = Bus::new();
+        let mut cpu = CPU::new();
+        let val: i8 = 0b00000001;
+        cpu.registers.set(Register::A, val as u16);
+        cpu.registers.set_flag(FlagRegister::Carry, true);
+        cpu.exec(Opcode::PrefixCB(Box::new(Opcode::SLA(Register::A))), &mut bus);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), ((val << 7) as u8) == 0);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), get_bit(((val << 7) as u8)));
+        assert_eq!(cpu.registers.get(Register::A), (val << 7) as u16);
+        assert_eq!(cpu.registers.get(Register::PC), 0x102);
+
+        let mut cpu = CPU::new();
+        let addr = 0xC000;
+        bus.write(addr, 0b00000010);
+        cpu.registers.set(Register::HL, addr);
+        cpu.registers.set_flag(FlagRegister::Carry, false);
+        cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RL(Register::HL))), &mut bus);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
+        assert_eq!(bus.read(addr), 0b00000000);
+        assert_eq!(cpu.registers.get(Register::PC), 0x102); */
+    }
+
+    #[test]
+    fn test_prefix_cb_sra_instruction() {
+        /* let mut bus = Bus::new();
+        let mut cpu = CPU::new();
+        cpu.registers.set(Register::A, 0b00000001);
+        cpu.registers.set_flag(FlagRegister::Carry, true);
+        cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RR(Register::A))), &mut bus);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
+        assert_eq!(cpu.registers.get(Register::A), 0b00000110);
+        assert_eq!(cpu.registers.get(Register::PC), 0x102);
+
+        let mut cpu = CPU::new();
+        let addr = 0xC000;
+        bus.write(addr, 0b01000000);
+        cpu.registers.set(Register::HL, addr);
+        cpu.registers.set_flag(FlagRegister::Carry, false);
+        cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RR(Register::HL))), &mut bus);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
+        assert_eq!(bus.read(addr), 0b00000000);
+        assert_eq!(cpu.registers.get(Register::PC), 0x102); */
+    }
+
     #[test]
     fn test_nop_instructions() {
         let mut cpu = CPU::new();