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Basic MBC2 implementation
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commit
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@ -14,10 +14,9 @@ Any help or suggestion is welcome!
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- [x] Render the pixels
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- [x] Render the pixels
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- [ ] MBC Implementations
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- [ ] MBC Implementations
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- [x] NoMBC
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- [x] NoMBC
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- [ ] MBC1
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- [x] MBC1
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- [ ] MBC2
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- [x] MBC2
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- [ ] MBC3
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- [ ] MBC3
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- [ ] MBC4
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- [ ] MBC5
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- [ ] MBC5
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- [ ] MBC6
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- [ ] MBC6
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- [ ] MBC7
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- [ ] MBC7
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73
src/rom.rs
73
src/rom.rs
@ -63,6 +63,7 @@ pub fn load_rom(filename: &str) -> std::io::Result<Box<dyn ROM>> {
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Ok(match info.mbc {
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Ok(match info.mbc {
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MBC::NoMBC => Box::new(NoMBC::new(data, info)),
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MBC::NoMBC => Box::new(NoMBC::new(data, info)),
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MBC::MBC1 => Box::new(MBC1::new(data, info)),
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MBC::MBC1 => Box::new(MBC1::new(data, info)),
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MBC::MBC2 => Box::new(MBC2::new(data, info)),
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_ => unimplemented!(),
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_ => unimplemented!(),
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})
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})
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}
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}
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@ -323,3 +324,75 @@ impl ROM for MBC1 {
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}
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}
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}
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}
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}
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}
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pub struct MBC2 {
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data: Vec<u8>,
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info: ROMInfo,
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ram: Vec<u8>,
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rom_bank: u16,
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ram_bank: u8,
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ram_enable: bool,
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}
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impl MBC2 {
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fn new(data: Vec<u8>, info: ROMInfo) -> Self {
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println!("MBC {:?}", info.mbc);
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println!("Region {:?}", info.region);
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println!("Has RAM {}", info.has_ram);
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println!("ROM banks {}", info.rom_banks);
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println!("RAM banks {}", info.ram_banks);
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let ram = Vec::with_capacity(info.ram_size() as usize);
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Self {
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data,
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info,
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ram,
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rom_bank: 1,
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ram_bank: 0,
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ram_enable: false,
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}
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}
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fn switch_rom_bank(&mut self, bank: u16) {
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self.rom_bank = bank;
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if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
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self.rom_bank = self.info.rom_banks.saturating_sub(1);
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}
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if self.rom_bank == 0 {
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self.rom_bank = 1;
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}
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}
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}
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impl ROM for MBC2 {
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fn read(&self, address: u16) -> u8 {
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if BANK_ZERO.contains(&address) {
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return self.data[address as usize];
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} else if BANK_SWITCHABLE.contains(&address) {
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return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
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} else if address >= 0xA000 && address <= 0xA1FF {
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if !self.info.has_ram || !self.ram_enable {
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return 0xFF;
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}
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return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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} else if address >= 0xA200 && address <= 0xBFFF {
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return self.read(0xA000 + (address % 0x0200));
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}
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return 0xFF;
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}
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fn write(&mut self, address: u16, data: u8) {
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if BANK_SWITCHABLE.contains(&address) {
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if address.to_be_bytes()[0] & 1 == 0 {
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match data {
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0x0A => self.ram_enable = true,
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_ => self.ram_enable = false,
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}
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} else {
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self.switch_rom_bank(data as u16);
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}
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}
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}
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}
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