From a69c5be762e788727a9a3c2629458025550f78d1 Mon Sep 17 00:00:00 2001 From: Franco Colmenarez Date: Tue, 11 Oct 2022 20:34:01 -0500 Subject: [PATCH] WIP cgb double speed switch --- src/bus.rs | 27 ++ src/cpu.rs | 1059 ++++++++++++++++++++++++----------------------- src/emulator.rs | 5 +- src/ppu.rs | 16 +- src/render.rs | 2 +- src/sound.rs | 4 +- src/timer.rs | 16 +- 7 files changed, 590 insertions(+), 539 deletions(-) diff --git a/src/bus.rs b/src/bus.rs index 8f15e19..2b3a149 100644 --- a/src/bus.rs +++ b/src/bus.rs @@ -27,6 +27,7 @@ pub const SPRITE_ATTRIBUTE_TABLE: RangeInclusive = 0xFE00..=0xFE9F; pub const NOT_USABLE: RangeInclusive = 0xFEA0..=0xFEFF; pub const IO_REGISTERS: RangeInclusive = 0xFF00..=0xFF7F; pub const HIGH_RAM: RangeInclusive = 0xFF80..=0xFFFE; +pub const PREPARE_SPEED_SWITCH_ADDRESS: u16 = 0xFF4D; pub struct Bus { data: [u8; 0x10000], @@ -38,6 +39,8 @@ pub struct Bus { pub sound: Sound, pub interrupts: Interrupts, pub cgb_mode: bool, + pub double_speed_mode: bool, + pub prepare_double_speed_mode: bool, } impl Bus { @@ -70,6 +73,8 @@ impl Bus { sound: Sound::new(), interrupts: Interrupts::new(), cgb_mode, + double_speed_mode: false, + prepare_double_speed_mode: false, }; // Hardware registers after the bootrom @@ -119,6 +124,11 @@ impl Bus { return self.joypad.read(self.data[address as usize]); } else if Timer::is_io_register(address) { return self.timer.get_register(address); + } else if address == PREPARE_SPEED_SWITCH_ADDRESS && self.cgb_mode { + let byte = self.data[address as usize]; + let current_speed = (self.double_speed_mode as u8) << 7; + let prepare_speed_switch = self.prepare_double_speed_mode as u8; + return (byte & 0b0111_1110) | current_speed | prepare_speed_switch; } self.data[address as usize] } @@ -161,6 +171,11 @@ impl Bus { self.hdma_transfer(data); } else if PPU::is_io_register(address) { self.ppu.set_register(address, data); + } else if address == PREPARE_SPEED_SWITCH_ADDRESS && self.cgb_mode { + let current_byte = self.data[address as usize]; + self.prepare_double_speed_mode = (data & 1) == 1; + // bit 7 is read only on cgb mode + self.data[address as usize] = (current_byte & 0b1000_0000) | (data & 0b0111_1111); } else { self.data[address as usize] = data; } @@ -172,6 +187,18 @@ impl Bus { self.write(address.wrapping_add(1), bytes[1]); } + pub fn prepare_double_speed_mode(&self) -> bool { + self.cgb_mode && self.prepare_double_speed_mode + } + + pub fn double_speed_mode(&self) -> bool { + self.cgb_mode && self.double_speed_mode + } + + pub fn set_double_speed_mode(&mut self, val: bool) { + self.double_speed_mode = val; + } + fn dma_transfer(&mut self, data: u8) { let source = (data as u16) * 0x100; let mut count: u16 = 0; diff --git a/src/cpu.rs b/src/cpu.rs index 1f6a937..ab10eec 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -8,7 +8,10 @@ use crate::utils::{ sub_half_carry, add_half_carry_16bit, }; -use crate::bus::Bus; +use crate::bus::{ + Bus, + PREPARE_SPEED_SWITCH_ADDRESS, +}; use crate::interrupts::{ Interrupt, INTERRUPT_ENABLE_ADDRESS, @@ -238,519 +241,519 @@ impl OpcodeParameterBytes { let opcode = self.0; let two_byte_param = join_bytes(self.2, self.1); match opcode { - 0x06 => (Opcode::LD(OpcodeParameter::Register_U8(Register::B, self.1)), Cycles(2)), - 0x0E => (Opcode::LD(OpcodeParameter::Register_U8(Register::C, self.1)), Cycles(2)), - 0x16 => (Opcode::LD(OpcodeParameter::Register_U8(Register::D, self.1)), Cycles(2)), - 0x1E => (Opcode::LD(OpcodeParameter::Register_U8(Register::E, self.1)), Cycles(2)), - 0x26 => (Opcode::LD(OpcodeParameter::Register_U8(Register::H, self.1)), Cycles(2)), - 0x2E => (Opcode::LD(OpcodeParameter::Register_U8(Register::L, self.1)), Cycles(2)), - 0x7F => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0x78 => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0x79 => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0x7A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0x7B => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0x7C => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0x7D => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0x7E => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0x40 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::B)), Cycles(1)), - 0x41 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::C)), Cycles(1)), - 0x42 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::D)), Cycles(1)), - 0x43 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::E)), Cycles(1)), - 0x44 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::H)), Cycles(1)), - 0x45 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::L)), Cycles(1)), - 0x46 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::HL)), Cycles(2)), - 0x48 => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::B)), Cycles(1)), - 0x49 => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::C)), Cycles(1)), - 0x4A => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::D)), Cycles(1)), - 0x4B => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::E)), Cycles(1)), - 0x4C => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::H)), Cycles(1)), - 0x4D => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::L)), Cycles(1)), - 0x4E => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::HL)), Cycles(2)), - 0x50 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::B)), Cycles(1)), - 0x51 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::C)), Cycles(1)), - 0x52 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::D)), Cycles(1)), - 0x53 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::E)), Cycles(1)), - 0x54 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::H)), Cycles(1)), - 0x55 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::L)), Cycles(1)), - 0x56 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::HL)), Cycles(2)), - 0x58 => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::B)), Cycles(1)), - 0x59 => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::C)), Cycles(1)), - 0x5A => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::D)), Cycles(1)), - 0x5B => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::E)), Cycles(1)), - 0x5C => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::H)), Cycles(1)), - 0x5D => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::L)), Cycles(1)), - 0x5E => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::HL)), Cycles(2)), - 0x60 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::B)), Cycles(1)), - 0x61 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::C)), Cycles(1)), - 0x62 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::D)), Cycles(1)), - 0x63 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::E)), Cycles(1)), - 0x64 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::H)), Cycles(1)), - 0x65 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::L)), Cycles(1)), - 0x66 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::HL)), Cycles(2)), - 0x68 => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::B)), Cycles(1)), - 0x69 => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::C)), Cycles(1)), - 0x6A => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::D)), Cycles(1)), - 0x6B => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::E)), Cycles(1)), - 0x6C => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::H)), Cycles(1)), - 0x6D => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::L)), Cycles(1)), - 0x6E => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::HL)), Cycles(2)), - 0x70 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::B)), Cycles(2)), - 0x71 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::C)), Cycles(2)), - 0x72 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::D)), Cycles(2)), - 0x73 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::E)), Cycles(2)), - 0x74 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::H)), Cycles(2)), - 0x75 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::L)), Cycles(2)), - 0x47 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::A)), Cycles(1)), - 0x4F => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::A)), Cycles(1)), - 0x57 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::A)), Cycles(1)), - 0x5F => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::A)), Cycles(1)), - 0x67 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::A)), Cycles(1)), - 0x6F => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::A)), Cycles(1)), - 0x02 => (Opcode::LD(OpcodeParameter::Register_Register(Register::BC, Register::A)), Cycles(2)), - 0x12 => (Opcode::LD(OpcodeParameter::Register_Register(Register::DE, Register::A)), Cycles(2)), - 0x77 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::A)), Cycles(2)), - 0x36 => (Opcode::LD(OpcodeParameter::Register_U8(Register::HL, self.1)), Cycles(3)), - 0x0A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::BC)), Cycles(2)), - 0x1A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::DE)), Cycles(2)), - 0xFA => (Opcode::LD(OpcodeParameter::Register_U16(Register::A, two_byte_param)), Cycles(4)), - 0x3E => (Opcode::LD(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), - 0xEA => (Opcode::LD(OpcodeParameter::U16_Register(two_byte_param, Register::A)), Cycles(4)), - 0xF2 => (Opcode::LD(OpcodeParameter::Register_FF00plusRegister(Register::A, Register::C)), Cycles(2)), - 0xE2 => (Opcode::LD(OpcodeParameter::FF00plusRegister_Register(Register::C, Register::A)), Cycles(2)), - 0x3A => (Opcode::LDD(OpcodeParameter::Register_RegisterDecrement(Register::A, Register::HL)), Cycles(2)), - 0x32 => (Opcode::LDD(OpcodeParameter::RegisterDecrement_Register(Register::HL, Register::A)), Cycles(2)), - 0x2A => (Opcode::LDI(OpcodeParameter::Register_RegisterIncrement(Register::A, Register::HL)), Cycles(2)), - 0x22 => (Opcode::LDI(OpcodeParameter::RegisterIncrement_Register(Register::HL, Register::A)), Cycles(2)), - 0xE0 => (Opcode::LD(OpcodeParameter::FF00plusU8_Register(self.1, Register::A)), Cycles(3)), - 0xF0 => (Opcode::LD(OpcodeParameter::Register_FF00plusU8(Register::A, self.1)), Cycles(3)), - 0x01 => (Opcode::LD(OpcodeParameter::Register_U16(Register::BC, two_byte_param)), Cycles(3)), - 0x11 => (Opcode::LD(OpcodeParameter::Register_U16(Register::DE, two_byte_param)), Cycles(3)), - 0x21 => (Opcode::LD(OpcodeParameter::Register_U16(Register::HL, two_byte_param)), Cycles(3)), - 0x31 => (Opcode::LD(OpcodeParameter::Register_U16(Register::SP, two_byte_param)), Cycles(3)), - 0xF9 => (Opcode::LD(OpcodeParameter::Register_Register(Register::SP, Register::HL)), Cycles(2)), - 0xF8 => (Opcode::LD(OpcodeParameter::Register_RegisterPlusI8(Register::HL, Register::SP, self.1 as i8)), Cycles(3)), - 0x08 => (Opcode::LD(OpcodeParameter::U16_Register(two_byte_param, Register::SP)), Cycles(5)), - 0xC5 => (Opcode::PUSH(Register::BC), Cycles(4)), - 0xD5 => (Opcode::PUSH(Register::DE), Cycles(4)), - 0xE5 => (Opcode::PUSH(Register::HL), Cycles(4)), - 0xF5 => (Opcode::PUSH(Register::AF), Cycles(4)), - 0xC1 => (Opcode::POP(Register::BC), Cycles(3)), - 0xD1 => (Opcode::POP(Register::DE), Cycles(3)), - 0xE1 => (Opcode::POP(Register::HL), Cycles(3)), - 0xF1 => (Opcode::POP(Register::AF), Cycles(3)), - 0x87 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0x80 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0x81 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0x82 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0x83 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0x84 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0x85 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0x86 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xC6 => (Opcode::ADD(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), - 0x09 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::BC)), Cycles(2)), - 0x19 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::DE)), Cycles(2)), - 0x29 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::HL)), Cycles(2)), - 0x39 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::SP)), Cycles(2)), - 0xE8 => (Opcode::ADD(OpcodeParameter::Register_I8(Register::SP, self.1 as i8)), Cycles(4)), - 0x8F => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0x88 => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0x89 => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0x8A => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0x8B => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0x8C => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0x8D => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0x8E => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xCE => (Opcode::ADC(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), - 0x97 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0x90 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0x91 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0x92 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0x93 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0x94 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0x95 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0x96 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xD6 => (Opcode::SUB(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), - 0x9F => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0x98 => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0x99 => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0x9A => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0x9B => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0x9C => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0x9D => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0x9E => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xDE => (Opcode::SBC(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), - 0xA7 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0xA0 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0xA1 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0xA2 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0xA3 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0xA4 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0xA5 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0xA6 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xE6 => (Opcode::AND(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), - 0xB7 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0xB0 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0xB1 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0xB2 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0xB3 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0xB4 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0xB5 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0xB6 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xF6 => (Opcode::OR(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), - 0xAF => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0xA8 => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0xA9 => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0xAA => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0xAB => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0xAC => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0xAD => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0xAE => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xEE => (Opcode::XOR(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), - 0xBF => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1)), - 0xB8 => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1)), - 0xB9 => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1)), - 0xBA => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1)), - 0xBB => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1)), - 0xBC => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1)), - 0xBD => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1)), - 0xBE => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2)), - 0xFE => (Opcode::CP(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2)), - 0x3C => (Opcode::INC(true, false, Register::A), Cycles(1)), - 0x04 => (Opcode::INC(true, false, Register::B), Cycles(1)), - 0x0C => (Opcode::INC(true, false, Register::C), Cycles(1)), - 0x14 => (Opcode::INC(true, false, Register::D), Cycles(1)), - 0x1C => (Opcode::INC(true, false, Register::E), Cycles(1)), - 0x24 => (Opcode::INC(true, false, Register::H), Cycles(1)), - 0x2C => (Opcode::INC(true, false, Register::L), Cycles(1)), - 0x34 => (Opcode::INC(true, true, Register::HL), Cycles(3)), - 0x03 => (Opcode::INC(false, false, Register::BC), Cycles(2)), - 0x13 => (Opcode::INC(false, false, Register::DE), Cycles(2)), - 0x23 => (Opcode::INC(false, false, Register::HL), Cycles(2)), - 0x33 => (Opcode::INC(false, false, Register::SP), Cycles(2)), - 0x3D => (Opcode::DEC(true, false, Register::A), Cycles(1)), - 0x05 => (Opcode::DEC(true, false, Register::B), Cycles(1)), - 0x0D => (Opcode::DEC(true, false, Register::C), Cycles(1)), - 0x15 => (Opcode::DEC(true, false, Register::D), Cycles(1)), - 0x1D => (Opcode::DEC(true, false, Register::E), Cycles(1)), - 0x25 => (Opcode::DEC(true, false, Register::H), Cycles(1)), - 0x2D => (Opcode::DEC(true, false, Register::L), Cycles(1)), - 0x35 => (Opcode::DEC(true, true, Register::HL), Cycles(3)), - 0x0B => (Opcode::DEC(false, false, Register::BC), Cycles(2)), - 0x1B => (Opcode::DEC(false, false, Register::DE), Cycles(2)), - 0x2B => (Opcode::DEC(false, false, Register::HL), Cycles(2)), - 0x3B => (Opcode::DEC(false, false, Register::SP), Cycles(2)), - 0x27 => (Opcode::DAA, Cycles(1)), - 0x2F => (Opcode::CPL, Cycles(1)), - 0x3F => (Opcode::CCF, Cycles(1)), - 0x37 => (Opcode::SCF, Cycles(1)), - 0x17 => (Opcode::RLA, Cycles(1)), - 0x07 => (Opcode::RLCA, Cycles(1)), - 0x0F => (Opcode::RRCA, Cycles(1)), - 0x1F => (Opcode::RRA, Cycles(1)), + 0x06 => (Opcode::LD(OpcodeParameter::Register_U8(Register::B, self.1)), Cycles(2.0)), + 0x0E => (Opcode::LD(OpcodeParameter::Register_U8(Register::C, self.1)), Cycles(2.0)), + 0x16 => (Opcode::LD(OpcodeParameter::Register_U8(Register::D, self.1)), Cycles(2.0)), + 0x1E => (Opcode::LD(OpcodeParameter::Register_U8(Register::E, self.1)), Cycles(2.0)), + 0x26 => (Opcode::LD(OpcodeParameter::Register_U8(Register::H, self.1)), Cycles(2.0)), + 0x2E => (Opcode::LD(OpcodeParameter::Register_U8(Register::L, self.1)), Cycles(2.0)), + 0x7F => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1.0)), + 0x78 => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1.0)), + 0x79 => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1.0)), + 0x7A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1.0)), + 0x7B => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1.0)), + 0x7C => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1.0)), + 0x7D => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1.0)), + 0x7E => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2.0)), + 0x40 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::B)), Cycles(1.0)), + 0x41 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::C)), Cycles(1.0)), + 0x42 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::D)), Cycles(1.0)), + 0x43 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::E)), Cycles(1.0)), + 0x44 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::H)), Cycles(1.0)), + 0x45 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::L)), Cycles(1.0)), + 0x46 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::HL)), Cycles(2.0)), + 0x48 => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::B)), Cycles(1.0)), + 0x49 => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::C)), Cycles(1.0)), + 0x4A => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::D)), Cycles(1.0)), + 0x4B => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::E)), Cycles(1.0)), + 0x4C => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::H)), Cycles(1.0)), + 0x4D => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::L)), Cycles(1.0)), + 0x4E => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::HL)), Cycles(2.0)), + 0x50 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::B)), Cycles(1.0)), + 0x51 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::C)), Cycles(1.0)), + 0x52 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::D)), Cycles(1.0)), + 0x53 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::E)), Cycles(1.0)), + 0x54 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::H)), Cycles(1.0)), + 0x55 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::L)), Cycles(1.0)), + 0x56 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::HL)), Cycles(2.0)), + 0x58 => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::B)), Cycles(1.0)), + 0x59 => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::C)), Cycles(1.0)), + 0x5A => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::D)), Cycles(1.0)), + 0x5B => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::E)), Cycles(1.0)), + 0x5C => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::H)), Cycles(1.0)), + 0x5D => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::L)), Cycles(1.0)), + 0x5E => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::HL)), Cycles(2.0)), + 0x60 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::B)), Cycles(1.0)), + 0x61 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::C)), Cycles(1.0)), + 0x62 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::D)), Cycles(1.0)), + 0x63 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::E)), Cycles(1.0)), + 0x64 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::H)), Cycles(1.0)), + 0x65 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::L)), Cycles(1.0)), + 0x66 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::HL)), Cycles(2.0)), + 0x68 => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::B)), Cycles(1.0)), + 0x69 => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::C)), Cycles(1.0)), + 0x6A => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::D)), Cycles(1.0)), + 0x6B => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::E)), Cycles(1.0)), + 0x6C => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::H)), Cycles(1.0)), + 0x6D => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::L)), Cycles(1.0)), + 0x6E => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::HL)), Cycles(2.0)), + 0x70 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::B)), Cycles(2.0)), + 0x71 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::C)), Cycles(2.0)), + 0x72 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::D)), Cycles(2.0)), + 0x73 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::E)), Cycles(2.0)), + 0x74 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::H)), Cycles(2.0)), + 0x75 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::L)), Cycles(2.0)), + 0x47 => (Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::A)), Cycles(1.0)), + 0x4F => (Opcode::LD(OpcodeParameter::Register_Register(Register::C, Register::A)), Cycles(1.0)), + 0x57 => (Opcode::LD(OpcodeParameter::Register_Register(Register::D, Register::A)), Cycles(1.0)), + 0x5F => (Opcode::LD(OpcodeParameter::Register_Register(Register::E, Register::A)), Cycles(1.0)), + 0x67 => (Opcode::LD(OpcodeParameter::Register_Register(Register::H, Register::A)), Cycles(1.0)), + 0x6F => (Opcode::LD(OpcodeParameter::Register_Register(Register::L, Register::A)), Cycles(1.0)), + 0x02 => (Opcode::LD(OpcodeParameter::Register_Register(Register::BC, Register::A)), Cycles(2.0)), + 0x12 => (Opcode::LD(OpcodeParameter::Register_Register(Register::DE, Register::A)), Cycles(2.0)), + 0x77 => (Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::A)), Cycles(2.0)), + 0x36 => (Opcode::LD(OpcodeParameter::Register_U8(Register::HL, self.1)), Cycles(3.0)), + 0x0A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::BC)), Cycles(2.0)), + 0x1A => (Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::DE)), Cycles(2.0)), + 0xFA => (Opcode::LD(OpcodeParameter::Register_U16(Register::A, two_byte_param)), Cycles(4.0)), + 0x3E => (Opcode::LD(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2.0)), + 0xEA => (Opcode::LD(OpcodeParameter::U16_Register(two_byte_param, Register::A)), Cycles(4.0)), + 0xF2 => (Opcode::LD(OpcodeParameter::Register_FF00plusRegister(Register::A, Register::C)), Cycles(2.0)), + 0xE2 => (Opcode::LD(OpcodeParameter::FF00plusRegister_Register(Register::C, Register::A)), Cycles(2.0)), + 0x3A => (Opcode::LDD(OpcodeParameter::Register_RegisterDecrement(Register::A, Register::HL)), Cycles(2.0)), + 0x32 => (Opcode::LDD(OpcodeParameter::RegisterDecrement_Register(Register::HL, Register::A)), Cycles(2.0)), + 0x2A => (Opcode::LDI(OpcodeParameter::Register_RegisterIncrement(Register::A, Register::HL)), Cycles(2.0)), + 0x22 => (Opcode::LDI(OpcodeParameter::RegisterIncrement_Register(Register::HL, Register::A)), Cycles(2.0)), + 0xE0 => (Opcode::LD(OpcodeParameter::FF00plusU8_Register(self.1, Register::A)), Cycles(3.0)), + 0xF0 => (Opcode::LD(OpcodeParameter::Register_FF00plusU8(Register::A, self.1)), Cycles(3.0)), + 0x01 => (Opcode::LD(OpcodeParameter::Register_U16(Register::BC, two_byte_param)), Cycles(3.0)), + 0x11 => (Opcode::LD(OpcodeParameter::Register_U16(Register::DE, two_byte_param)), Cycles(3.0)), + 0x21 => (Opcode::LD(OpcodeParameter::Register_U16(Register::HL, two_byte_param)), Cycles(3.0)), + 0x31 => (Opcode::LD(OpcodeParameter::Register_U16(Register::SP, two_byte_param)), Cycles(3.0)), + 0xF9 => (Opcode::LD(OpcodeParameter::Register_Register(Register::SP, Register::HL)), Cycles(2.0)), + 0xF8 => (Opcode::LD(OpcodeParameter::Register_RegisterPlusI8(Register::HL, Register::SP, self.1 as i8)), Cycles(3.0)), + 0x08 => (Opcode::LD(OpcodeParameter::U16_Register(two_byte_param, Register::SP)), Cycles(5.0)), + 0xC5 => (Opcode::PUSH(Register::BC), Cycles(4.0)), + 0xD5 => (Opcode::PUSH(Register::DE), Cycles(4.0)), + 0xE5 => (Opcode::PUSH(Register::HL), Cycles(4.0)), + 0xF5 => (Opcode::PUSH(Register::AF), Cycles(4.0)), + 0xC1 => (Opcode::POP(Register::BC), Cycles(3.0)), + 0xD1 => (Opcode::POP(Register::DE), Cycles(3.0)), + 0xE1 => (Opcode::POP(Register::HL), Cycles(3.0)), + 0xF1 => (Opcode::POP(Register::AF), Cycles(3.0)), + 0x87 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1.0)), + 0x80 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1.0)), + 0x81 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1.0)), + 0x82 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1.0)), + 0x83 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1.0)), + 0x84 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1.0)), + 0x85 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1.0)), + 0x86 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2.0)), + 0xC6 => (Opcode::ADD(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2.0)), + 0x09 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::BC)), Cycles(2.0)), + 0x19 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::DE)), Cycles(2.0)), + 0x29 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::HL)), Cycles(2.0)), + 0x39 => (Opcode::ADD(OpcodeParameter::Register_Register(Register::HL, Register::SP)), Cycles(2.0)), + 0xE8 => (Opcode::ADD(OpcodeParameter::Register_I8(Register::SP, self.1 as i8)), Cycles(4.0)), + 0x8F => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1.0)), + 0x88 => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1.0)), + 0x89 => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1.0)), + 0x8A => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1.0)), + 0x8B => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1.0)), + 0x8C => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1.0)), + 0x8D => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1.0)), + 0x8E => (Opcode::ADC(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2.0)), + 0xCE => (Opcode::ADC(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2.0)), + 0x97 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1.0)), + 0x90 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1.0)), + 0x91 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1.0)), + 0x92 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1.0)), + 0x93 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1.0)), + 0x94 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1.0)), + 0x95 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1.0)), + 0x96 => (Opcode::SUB(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2.0)), + 0xD6 => (Opcode::SUB(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2.0)), + 0x9F => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1.0)), + 0x98 => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1.0)), + 0x99 => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1.0)), + 0x9A => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1.0)), + 0x9B => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1.0)), + 0x9C => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1.0)), + 0x9D => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1.0)), + 0x9E => (Opcode::SBC(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2.0)), + 0xDE => (Opcode::SBC(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2.0)), + 0xA7 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1.0)), + 0xA0 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1.0)), + 0xA1 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1.0)), + 0xA2 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1.0)), + 0xA3 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1.0)), + 0xA4 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1.0)), + 0xA5 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1.0)), + 0xA6 => (Opcode::AND(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2.0)), + 0xE6 => (Opcode::AND(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2.0)), + 0xB7 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1.0)), + 0xB0 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1.0)), + 0xB1 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1.0)), + 0xB2 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1.0)), + 0xB3 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1.0)), + 0xB4 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1.0)), + 0xB5 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1.0)), + 0xB6 => (Opcode::OR(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2.0)), + 0xF6 => (Opcode::OR(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2.0)), + 0xAF => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1.0)), + 0xA8 => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1.0)), + 0xA9 => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1.0)), + 0xAA => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1.0)), + 0xAB => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1.0)), + 0xAC => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1.0)), + 0xAD => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1.0)), + 0xAE => (Opcode::XOR(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2.0)), + 0xEE => (Opcode::XOR(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2.0)), + 0xBF => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::A)), Cycles(1.0)), + 0xB8 => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::B)), Cycles(1.0)), + 0xB9 => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::C)), Cycles(1.0)), + 0xBA => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::D)), Cycles(1.0)), + 0xBB => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::E)), Cycles(1.0)), + 0xBC => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::H)), Cycles(1.0)), + 0xBD => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::L)), Cycles(1.0)), + 0xBE => (Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::HL)), Cycles(2.0)), + 0xFE => (Opcode::CP(OpcodeParameter::Register_U8(Register::A, self.1)), Cycles(2.0)), + 0x3C => (Opcode::INC(true, false, Register::A), Cycles(1.0)), + 0x04 => (Opcode::INC(true, false, Register::B), Cycles(1.0)), + 0x0C => (Opcode::INC(true, false, Register::C), Cycles(1.0)), + 0x14 => (Opcode::INC(true, false, Register::D), Cycles(1.0)), + 0x1C => (Opcode::INC(true, false, Register::E), Cycles(1.0)), + 0x24 => (Opcode::INC(true, false, Register::H), Cycles(1.0)), + 0x2C => (Opcode::INC(true, false, Register::L), Cycles(1.0)), + 0x34 => (Opcode::INC(true, true, Register::HL), Cycles(3.0)), + 0x03 => (Opcode::INC(false, false, Register::BC), Cycles(2.0)), + 0x13 => (Opcode::INC(false, false, Register::DE), Cycles(2.0)), + 0x23 => (Opcode::INC(false, false, Register::HL), Cycles(2.0)), + 0x33 => (Opcode::INC(false, false, Register::SP), Cycles(2.0)), + 0x3D => (Opcode::DEC(true, false, Register::A), Cycles(1.0)), + 0x05 => (Opcode::DEC(true, false, Register::B), Cycles(1.0)), + 0x0D => (Opcode::DEC(true, false, Register::C), Cycles(1.0)), + 0x15 => (Opcode::DEC(true, false, Register::D), Cycles(1.0)), + 0x1D => (Opcode::DEC(true, false, Register::E), Cycles(1.0)), + 0x25 => (Opcode::DEC(true, false, Register::H), Cycles(1.0)), + 0x2D => (Opcode::DEC(true, false, Register::L), Cycles(1.0)), + 0x35 => (Opcode::DEC(true, true, Register::HL), Cycles(3.0)), + 0x0B => (Opcode::DEC(false, false, Register::BC), Cycles(2.0)), + 0x1B => (Opcode::DEC(false, false, Register::DE), Cycles(2.0)), + 0x2B => (Opcode::DEC(false, false, Register::HL), Cycles(2.0)), + 0x3B => (Opcode::DEC(false, false, Register::SP), Cycles(2.0)), + 0x27 => (Opcode::DAA, Cycles(1.0)), + 0x2F => (Opcode::CPL, Cycles(1.0)), + 0x3F => (Opcode::CCF, Cycles(1.0)), + 0x37 => (Opcode::SCF, Cycles(1.0)), + 0x17 => (Opcode::RLA, Cycles(1.0)), + 0x07 => (Opcode::RLCA, Cycles(1.0)), + 0x0F => (Opcode::RRCA, Cycles(1.0)), + 0x1F => (Opcode::RRA, Cycles(1.0)), 0xCB => match self.1 { - 0x00 => (Opcode::PrefixCB(CBOpcode::RLC(Register::B)), Cycles(2)), - 0x01 => (Opcode::PrefixCB(CBOpcode::RLC(Register::C)), Cycles(2)), - 0x02 => (Opcode::PrefixCB(CBOpcode::RLC(Register::D)), Cycles(2)), - 0x03 => (Opcode::PrefixCB(CBOpcode::RLC(Register::E)), Cycles(2)), - 0x04 => (Opcode::PrefixCB(CBOpcode::RLC(Register::H)), Cycles(2)), - 0x05 => (Opcode::PrefixCB(CBOpcode::RLC(Register::L)), Cycles(2)), - 0x06 => (Opcode::PrefixCB(CBOpcode::RLC(Register::HL)), Cycles(4)), - 0x07 => (Opcode::PrefixCB(CBOpcode::RLC(Register::A)), Cycles(2)), + 0x00 => (Opcode::PrefixCB(CBOpcode::RLC(Register::B)), Cycles(2.0)), + 0x01 => (Opcode::PrefixCB(CBOpcode::RLC(Register::C)), Cycles(2.0)), + 0x02 => (Opcode::PrefixCB(CBOpcode::RLC(Register::D)), Cycles(2.0)), + 0x03 => (Opcode::PrefixCB(CBOpcode::RLC(Register::E)), Cycles(2.0)), + 0x04 => (Opcode::PrefixCB(CBOpcode::RLC(Register::H)), Cycles(2.0)), + 0x05 => (Opcode::PrefixCB(CBOpcode::RLC(Register::L)), Cycles(2.0)), + 0x06 => (Opcode::PrefixCB(CBOpcode::RLC(Register::HL)), Cycles(4.0)), + 0x07 => (Opcode::PrefixCB(CBOpcode::RLC(Register::A)), Cycles(2.0)), - 0x08 => (Opcode::PrefixCB(CBOpcode::RRC(Register::B)), Cycles(2)), - 0x09 => (Opcode::PrefixCB(CBOpcode::RRC(Register::C)), Cycles(2)), - 0x0A => (Opcode::PrefixCB(CBOpcode::RRC(Register::D)), Cycles(2)), - 0x0B => (Opcode::PrefixCB(CBOpcode::RRC(Register::E)), Cycles(2)), - 0x0C => (Opcode::PrefixCB(CBOpcode::RRC(Register::H)), Cycles(2)), - 0x0D => (Opcode::PrefixCB(CBOpcode::RRC(Register::L)), Cycles(2)), - 0x0E => (Opcode::PrefixCB(CBOpcode::RRC(Register::HL)), Cycles(4)), - 0x0F => (Opcode::PrefixCB(CBOpcode::RRC(Register::A)), Cycles(2)), + 0x08 => (Opcode::PrefixCB(CBOpcode::RRC(Register::B)), Cycles(2.0)), + 0x09 => (Opcode::PrefixCB(CBOpcode::RRC(Register::C)), Cycles(2.0)), + 0x0A => (Opcode::PrefixCB(CBOpcode::RRC(Register::D)), Cycles(2.0)), + 0x0B => (Opcode::PrefixCB(CBOpcode::RRC(Register::E)), Cycles(2.0)), + 0x0C => (Opcode::PrefixCB(CBOpcode::RRC(Register::H)), Cycles(2.0)), + 0x0D => (Opcode::PrefixCB(CBOpcode::RRC(Register::L)), Cycles(2.0)), + 0x0E => (Opcode::PrefixCB(CBOpcode::RRC(Register::HL)), Cycles(4.0)), + 0x0F => (Opcode::PrefixCB(CBOpcode::RRC(Register::A)), Cycles(2.0)), - 0x10 => (Opcode::PrefixCB(CBOpcode::RL(Register::B)), Cycles(2)), - 0x11 => (Opcode::PrefixCB(CBOpcode::RL(Register::C)), Cycles(2)), - 0x12 => (Opcode::PrefixCB(CBOpcode::RL(Register::D)), Cycles(2)), - 0x13 => (Opcode::PrefixCB(CBOpcode::RL(Register::E)), Cycles(2)), - 0x14 => (Opcode::PrefixCB(CBOpcode::RL(Register::H)), Cycles(2)), - 0x15 => (Opcode::PrefixCB(CBOpcode::RL(Register::L)), Cycles(2)), - 0x16 => (Opcode::PrefixCB(CBOpcode::RL(Register::HL)), Cycles(4)), - 0x17 => (Opcode::PrefixCB(CBOpcode::RL(Register::A)), Cycles(2)), + 0x10 => (Opcode::PrefixCB(CBOpcode::RL(Register::B)), Cycles(2.0)), + 0x11 => (Opcode::PrefixCB(CBOpcode::RL(Register::C)), Cycles(2.0)), + 0x12 => (Opcode::PrefixCB(CBOpcode::RL(Register::D)), Cycles(2.0)), + 0x13 => (Opcode::PrefixCB(CBOpcode::RL(Register::E)), Cycles(2.0)), + 0x14 => (Opcode::PrefixCB(CBOpcode::RL(Register::H)), Cycles(2.0)), + 0x15 => (Opcode::PrefixCB(CBOpcode::RL(Register::L)), Cycles(2.0)), + 0x16 => (Opcode::PrefixCB(CBOpcode::RL(Register::HL)), Cycles(4.0)), + 0x17 => (Opcode::PrefixCB(CBOpcode::RL(Register::A)), Cycles(2.0)), - 0x18 => (Opcode::PrefixCB(CBOpcode::RR(Register::B)), Cycles(2)), - 0x19 => (Opcode::PrefixCB(CBOpcode::RR(Register::C)), Cycles(2)), - 0x1A => (Opcode::PrefixCB(CBOpcode::RR(Register::D)), Cycles(2)), - 0x1B => (Opcode::PrefixCB(CBOpcode::RR(Register::E)), Cycles(2)), - 0x1C => (Opcode::PrefixCB(CBOpcode::RR(Register::H)), Cycles(2)), - 0x1D => (Opcode::PrefixCB(CBOpcode::RR(Register::L)), Cycles(2)), - 0x1E => (Opcode::PrefixCB(CBOpcode::RR(Register::HL)), Cycles(4)), - 0x1F => (Opcode::PrefixCB(CBOpcode::RR(Register::A)), Cycles(2)), + 0x18 => (Opcode::PrefixCB(CBOpcode::RR(Register::B)), Cycles(2.0)), + 0x19 => (Opcode::PrefixCB(CBOpcode::RR(Register::C)), Cycles(2.0)), + 0x1A => (Opcode::PrefixCB(CBOpcode::RR(Register::D)), Cycles(2.0)), + 0x1B => (Opcode::PrefixCB(CBOpcode::RR(Register::E)), Cycles(2.0)), + 0x1C => (Opcode::PrefixCB(CBOpcode::RR(Register::H)), Cycles(2.0)), + 0x1D => (Opcode::PrefixCB(CBOpcode::RR(Register::L)), Cycles(2.0)), + 0x1E => (Opcode::PrefixCB(CBOpcode::RR(Register::HL)), Cycles(4.0)), + 0x1F => (Opcode::PrefixCB(CBOpcode::RR(Register::A)), Cycles(2.0)), - 0x20 => (Opcode::PrefixCB(CBOpcode::SLA(Register::B)), Cycles(2)), - 0x21 => (Opcode::PrefixCB(CBOpcode::SLA(Register::C)), Cycles(2)), - 0x22 => (Opcode::PrefixCB(CBOpcode::SLA(Register::D)), Cycles(2)), - 0x23 => (Opcode::PrefixCB(CBOpcode::SLA(Register::E)), Cycles(2)), - 0x24 => (Opcode::PrefixCB(CBOpcode::SLA(Register::H)), Cycles(2)), - 0x25 => (Opcode::PrefixCB(CBOpcode::SLA(Register::L)), Cycles(2)), - 0x26 => (Opcode::PrefixCB(CBOpcode::SLA(Register::HL)), Cycles(4)), - 0x27 => (Opcode::PrefixCB(CBOpcode::SLA(Register::A)), Cycles(2)), + 0x20 => (Opcode::PrefixCB(CBOpcode::SLA(Register::B)), Cycles(2.0)), + 0x21 => (Opcode::PrefixCB(CBOpcode::SLA(Register::C)), Cycles(2.0)), + 0x22 => (Opcode::PrefixCB(CBOpcode::SLA(Register::D)), Cycles(2.0)), + 0x23 => (Opcode::PrefixCB(CBOpcode::SLA(Register::E)), Cycles(2.0)), + 0x24 => (Opcode::PrefixCB(CBOpcode::SLA(Register::H)), Cycles(2.0)), + 0x25 => (Opcode::PrefixCB(CBOpcode::SLA(Register::L)), Cycles(2.0)), + 0x26 => (Opcode::PrefixCB(CBOpcode::SLA(Register::HL)), Cycles(4.0)), + 0x27 => (Opcode::PrefixCB(CBOpcode::SLA(Register::A)), Cycles(2.0)), - 0x28 => (Opcode::PrefixCB(CBOpcode::SRA(Register::B)), Cycles(2)), - 0x29 => (Opcode::PrefixCB(CBOpcode::SRA(Register::C)), Cycles(2)), - 0x2A => (Opcode::PrefixCB(CBOpcode::SRA(Register::D)), Cycles(2)), - 0x2B => (Opcode::PrefixCB(CBOpcode::SRA(Register::E)), Cycles(2)), - 0x2C => (Opcode::PrefixCB(CBOpcode::SRA(Register::H)), Cycles(2)), - 0x2D => (Opcode::PrefixCB(CBOpcode::SRA(Register::L)), Cycles(2)), - 0x2E => (Opcode::PrefixCB(CBOpcode::SRA(Register::HL)), Cycles(4)), - 0x2F => (Opcode::PrefixCB(CBOpcode::SRA(Register::A)), Cycles(2)), + 0x28 => (Opcode::PrefixCB(CBOpcode::SRA(Register::B)), Cycles(2.0)), + 0x29 => (Opcode::PrefixCB(CBOpcode::SRA(Register::C)), Cycles(2.0)), + 0x2A => (Opcode::PrefixCB(CBOpcode::SRA(Register::D)), Cycles(2.0)), + 0x2B => (Opcode::PrefixCB(CBOpcode::SRA(Register::E)), Cycles(2.0)), + 0x2C => (Opcode::PrefixCB(CBOpcode::SRA(Register::H)), Cycles(2.0)), + 0x2D => (Opcode::PrefixCB(CBOpcode::SRA(Register::L)), Cycles(2.0)), + 0x2E => (Opcode::PrefixCB(CBOpcode::SRA(Register::HL)), Cycles(4.0)), + 0x2F => (Opcode::PrefixCB(CBOpcode::SRA(Register::A)), Cycles(2.0)), - 0x30 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::B)), Cycles(2)), - 0x31 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::C)), Cycles(2)), - 0x32 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::D)), Cycles(2)), - 0x33 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::E)), Cycles(2)), - 0x34 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::H)), Cycles(2)), - 0x35 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::L)), Cycles(2)), - 0x36 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::HL)), Cycles(4)), - 0x37 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::A)), Cycles(2)), + 0x30 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::B)), Cycles(2.0)), + 0x31 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::C)), Cycles(2.0)), + 0x32 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::D)), Cycles(2.0)), + 0x33 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::E)), Cycles(2.0)), + 0x34 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::H)), Cycles(2.0)), + 0x35 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::L)), Cycles(2.0)), + 0x36 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::HL)), Cycles(4.0)), + 0x37 => (Opcode::PrefixCB(CBOpcode::SWAP(Register::A)), Cycles(2.0)), - 0x38 => (Opcode::PrefixCB(CBOpcode::SRL(Register::B)), Cycles(2)), - 0x39 => (Opcode::PrefixCB(CBOpcode::SRL(Register::C)), Cycles(2)), - 0x3A => (Opcode::PrefixCB(CBOpcode::SRL(Register::D)), Cycles(2)), - 0x3B => (Opcode::PrefixCB(CBOpcode::SRL(Register::E)), Cycles(2)), - 0x3C => (Opcode::PrefixCB(CBOpcode::SRL(Register::H)), Cycles(2)), - 0x3D => (Opcode::PrefixCB(CBOpcode::SRL(Register::L)), Cycles(2)), - 0x3E => (Opcode::PrefixCB(CBOpcode::SRL(Register::HL)), Cycles(4)), - 0x3F => (Opcode::PrefixCB(CBOpcode::SRL(Register::A)), Cycles(2)), + 0x38 => (Opcode::PrefixCB(CBOpcode::SRL(Register::B)), Cycles(2.0)), + 0x39 => (Opcode::PrefixCB(CBOpcode::SRL(Register::C)), Cycles(2.0)), + 0x3A => (Opcode::PrefixCB(CBOpcode::SRL(Register::D)), Cycles(2.0)), + 0x3B => (Opcode::PrefixCB(CBOpcode::SRL(Register::E)), Cycles(2.0)), + 0x3C => (Opcode::PrefixCB(CBOpcode::SRL(Register::H)), Cycles(2.0)), + 0x3D => (Opcode::PrefixCB(CBOpcode::SRL(Register::L)), Cycles(2.0)), + 0x3E => (Opcode::PrefixCB(CBOpcode::SRL(Register::HL)), Cycles(4.0)), + 0x3F => (Opcode::PrefixCB(CBOpcode::SRL(Register::A)), Cycles(2.0)), - 0x40 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::B)), Cycles(2)), - 0x41 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::C)), Cycles(2)), - 0x42 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::D)), Cycles(2)), - 0x43 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::E)), Cycles(2)), - 0x44 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::H)), Cycles(2)), - 0x45 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::L)), Cycles(2)), - 0x46 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::HL)), Cycles(3)), - 0x47 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::A)), Cycles(2)), - 0x48 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::B)), Cycles(2)), - 0x49 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::C)), Cycles(2)), - 0x4A => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::D)), Cycles(2)), - 0x4B => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::E)), Cycles(2)), - 0x4C => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::H)), Cycles(2)), - 0x4D => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::L)), Cycles(2)), - 0x4E => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::HL)), Cycles(3)), - 0x4F => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::A)), Cycles(2)), - 0x50 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::B)), Cycles(2)), - 0x51 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::C)), Cycles(2)), - 0x52 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::D)), Cycles(2)), - 0x53 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::E)), Cycles(2)), - 0x54 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::H)), Cycles(2)), - 0x55 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::L)), Cycles(2)), - 0x56 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::HL)), Cycles(3)), - 0x57 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::A)), Cycles(2)), - 0x58 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::B)), Cycles(2)), - 0x59 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::C)), Cycles(2)), - 0x5A => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::D)), Cycles(2)), - 0x5B => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::E)), Cycles(2)), - 0x5C => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::H)), Cycles(2)), - 0x5D => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::L)), Cycles(2)), - 0x5E => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::HL)), Cycles(3)), - 0x5F => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::A)), Cycles(2)), - 0x60 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::B)), Cycles(2)), - 0x61 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::C)), Cycles(2)), - 0x62 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::D)), Cycles(2)), - 0x63 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::E)), Cycles(2)), - 0x64 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::H)), Cycles(2)), - 0x65 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::L)), Cycles(2)), - 0x66 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::HL)), Cycles(3)), - 0x67 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::A)), Cycles(2)), - 0x68 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::B)), Cycles(2)), - 0x69 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::C)), Cycles(2)), - 0x6A => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::D)), Cycles(2)), - 0x6B => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::E)), Cycles(2)), - 0x6C => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::H)), Cycles(2)), - 0x6D => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::L)), Cycles(2)), - 0x6E => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::HL)), Cycles(3)), - 0x6F => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::A)), Cycles(2)), - 0x70 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::B)), Cycles(2)), - 0x71 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::C)), Cycles(2)), - 0x72 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::D)), Cycles(2)), - 0x73 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::E)), Cycles(2)), - 0x74 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::H)), Cycles(2)), - 0x75 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::L)), Cycles(2)), - 0x76 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::HL)), Cycles(3)), - 0x77 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::A)), Cycles(2)), - 0x78 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::B)), Cycles(2)), - 0x79 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::C)), Cycles(2)), - 0x7A => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::D)), Cycles(2)), - 0x7B => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::E)), Cycles(2)), - 0x7C => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::H)), Cycles(2)), - 0x7D => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::L)), Cycles(2)), - 0x7E => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::HL)), Cycles(3)), - 0x7F => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::A)), Cycles(2)), + 0x40 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::B)), Cycles(2.0)), + 0x41 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::C)), Cycles(2.0)), + 0x42 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::D)), Cycles(2.0)), + 0x43 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::E)), Cycles(2.0)), + 0x44 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::H)), Cycles(2.0)), + 0x45 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::L)), Cycles(2.0)), + 0x46 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::HL)), Cycles(3.0)), + 0x47 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I0, Register::A)), Cycles(2.0)), + 0x48 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::B)), Cycles(2.0)), + 0x49 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::C)), Cycles(2.0)), + 0x4A => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::D)), Cycles(2.0)), + 0x4B => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::E)), Cycles(2.0)), + 0x4C => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::H)), Cycles(2.0)), + 0x4D => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::L)), Cycles(2.0)), + 0x4E => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::HL)), Cycles(3.0)), + 0x4F => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I1, Register::A)), Cycles(2.0)), + 0x50 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::B)), Cycles(2.0)), + 0x51 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::C)), Cycles(2.0)), + 0x52 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::D)), Cycles(2.0)), + 0x53 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::E)), Cycles(2.0)), + 0x54 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::H)), Cycles(2.0)), + 0x55 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::L)), Cycles(2.0)), + 0x56 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::HL)), Cycles(3.0)), + 0x57 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I2, Register::A)), Cycles(2.0)), + 0x58 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::B)), Cycles(2.0)), + 0x59 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::C)), Cycles(2.0)), + 0x5A => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::D)), Cycles(2.0)), + 0x5B => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::E)), Cycles(2.0)), + 0x5C => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::H)), Cycles(2.0)), + 0x5D => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::L)), Cycles(2.0)), + 0x5E => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::HL)), Cycles(3.0)), + 0x5F => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I3, Register::A)), Cycles(2.0)), + 0x60 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::B)), Cycles(2.0)), + 0x61 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::C)), Cycles(2.0)), + 0x62 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::D)), Cycles(2.0)), + 0x63 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::E)), Cycles(2.0)), + 0x64 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::H)), Cycles(2.0)), + 0x65 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::L)), Cycles(2.0)), + 0x66 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::HL)), Cycles(3.0)), + 0x67 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I4, Register::A)), Cycles(2.0)), + 0x68 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::B)), Cycles(2.0)), + 0x69 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::C)), Cycles(2.0)), + 0x6A => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::D)), Cycles(2.0)), + 0x6B => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::E)), Cycles(2.0)), + 0x6C => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::H)), Cycles(2.0)), + 0x6D => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::L)), Cycles(2.0)), + 0x6E => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::HL)), Cycles(3.0)), + 0x6F => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I5, Register::A)), Cycles(2.0)), + 0x70 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::B)), Cycles(2.0)), + 0x71 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::C)), Cycles(2.0)), + 0x72 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::D)), Cycles(2.0)), + 0x73 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::E)), Cycles(2.0)), + 0x74 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::H)), Cycles(2.0)), + 0x75 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::L)), Cycles(2.0)), + 0x76 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::HL)), Cycles(3.0)), + 0x77 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I6, Register::A)), Cycles(2.0)), + 0x78 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::B)), Cycles(2.0)), + 0x79 => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::C)), Cycles(2.0)), + 0x7A => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::D)), Cycles(2.0)), + 0x7B => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::E)), Cycles(2.0)), + 0x7C => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::H)), Cycles(2.0)), + 0x7D => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::L)), Cycles(2.0)), + 0x7E => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::HL)), Cycles(3.0)), + 0x7F => (Opcode::PrefixCB(CBOpcode::BIT(BitIndex::I7, Register::A)), Cycles(2.0)), - 0x80 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::B)), Cycles(2)), - 0x81 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::C)), Cycles(2)), - 0x82 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::D)), Cycles(2)), - 0x83 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::E)), Cycles(2)), - 0x84 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::H)), Cycles(2)), - 0x85 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::L)), Cycles(2)), - 0x86 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::HL)), Cycles(4)), - 0x87 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::A)), Cycles(2)), - 0x88 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::B)), Cycles(2)), - 0x89 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::C)), Cycles(2)), - 0x8A => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::D)), Cycles(2)), - 0x8B => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::E)), Cycles(2)), - 0x8C => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::H)), Cycles(2)), - 0x8D => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::L)), Cycles(2)), - 0x8E => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::HL)), Cycles(4)), - 0x8F => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::A)), Cycles(2)), - 0x90 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::B)), Cycles(2)), - 0x91 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::C)), Cycles(2)), - 0x92 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::D)), Cycles(2)), - 0x93 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::E)), Cycles(2)), - 0x94 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::H)), Cycles(2)), - 0x95 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::L)), Cycles(2)), - 0x96 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::HL)), Cycles(4)), - 0x97 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::A)), Cycles(2)), - 0x98 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::B)), Cycles(2)), - 0x99 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::C)), Cycles(2)), - 0x9A => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::D)), Cycles(2)), - 0x9B => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::E)), Cycles(2)), - 0x9C => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::H)), Cycles(2)), - 0x9D => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::L)), Cycles(2)), - 0x9E => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::HL)), Cycles(4)), - 0x9F => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::A)), Cycles(2)), - 0xA0 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::B)), Cycles(2)), - 0xA1 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::C)), Cycles(2)), - 0xA2 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::D)), Cycles(2)), - 0xA3 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::E)), Cycles(2)), - 0xA4 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::H)), Cycles(2)), - 0xA5 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::L)), Cycles(2)), - 0xA6 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::HL)), Cycles(4)), - 0xA7 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::A)), Cycles(2)), - 0xA8 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::B)), Cycles(2)), - 0xA9 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::C)), Cycles(2)), - 0xAA => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::D)), Cycles(2)), - 0xAB => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::E)), Cycles(2)), - 0xAC => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::H)), Cycles(2)), - 0xAD => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::L)), Cycles(2)), - 0xAE => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::HL)), Cycles(4)), - 0xAF => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::A)), Cycles(2)), - 0xB0 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::B)), Cycles(2)), - 0xB1 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::C)), Cycles(2)), - 0xB2 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::D)), Cycles(2)), - 0xB3 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::E)), Cycles(2)), - 0xB4 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::H)), Cycles(2)), - 0xB5 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::L)), Cycles(2)), - 0xB6 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::HL)), Cycles(4)), - 0xB7 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::A)), Cycles(2)), - 0xB8 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::B)), Cycles(2)), - 0xB9 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::C)), Cycles(2)), - 0xBA => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::D)), Cycles(2)), - 0xBB => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::E)), Cycles(2)), - 0xBC => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::H)), Cycles(2)), - 0xBD => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::L)), Cycles(2)), - 0xBE => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::HL)), Cycles(4)), - 0xBF => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::A)), Cycles(2)), + 0x80 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::B)), Cycles(2.0)), + 0x81 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::C)), Cycles(2.0)), + 0x82 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::D)), Cycles(2.0)), + 0x83 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::E)), Cycles(2.0)), + 0x84 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::H)), Cycles(2.0)), + 0x85 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::L)), Cycles(2.0)), + 0x86 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::HL)), Cycles(4.0)), + 0x87 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I0, Register::A)), Cycles(2.0)), + 0x88 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::B)), Cycles(2.0)), + 0x89 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::C)), Cycles(2.0)), + 0x8A => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::D)), Cycles(2.0)), + 0x8B => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::E)), Cycles(2.0)), + 0x8C => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::H)), Cycles(2.0)), + 0x8D => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::L)), Cycles(2.0)), + 0x8E => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::HL)), Cycles(4.0)), + 0x8F => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I1, Register::A)), Cycles(2.0)), + 0x90 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::B)), Cycles(2.0)), + 0x91 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::C)), Cycles(2.0)), + 0x92 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::D)), Cycles(2.0)), + 0x93 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::E)), Cycles(2.0)), + 0x94 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::H)), Cycles(2.0)), + 0x95 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::L)), Cycles(2.0)), + 0x96 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::HL)), Cycles(4.0)), + 0x97 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I2, Register::A)), Cycles(2.0)), + 0x98 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::B)), Cycles(2.0)), + 0x99 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::C)), Cycles(2.0)), + 0x9A => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::D)), Cycles(2.0)), + 0x9B => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::E)), Cycles(2.0)), + 0x9C => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::H)), Cycles(2.0)), + 0x9D => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::L)), Cycles(2.0)), + 0x9E => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::HL)), Cycles(4.0)), + 0x9F => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I3, Register::A)), Cycles(2.0)), + 0xA0 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::B)), Cycles(2.0)), + 0xA1 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::C)), Cycles(2.0)), + 0xA2 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::D)), Cycles(2.0)), + 0xA3 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::E)), Cycles(2.0)), + 0xA4 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::H)), Cycles(2.0)), + 0xA5 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::L)), Cycles(2.0)), + 0xA6 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::HL)), Cycles(4.0)), + 0xA7 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I4, Register::A)), Cycles(2.0)), + 0xA8 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::B)), Cycles(2.0)), + 0xA9 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::C)), Cycles(2.0)), + 0xAA => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::D)), Cycles(2.0)), + 0xAB => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::E)), Cycles(2.0)), + 0xAC => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::H)), Cycles(2.0)), + 0xAD => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::L)), Cycles(2.0)), + 0xAE => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::HL)), Cycles(4.0)), + 0xAF => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I5, Register::A)), Cycles(2.0)), + 0xB0 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::B)), Cycles(2.0)), + 0xB1 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::C)), Cycles(2.0)), + 0xB2 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::D)), Cycles(2.0)), + 0xB3 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::E)), Cycles(2.0)), + 0xB4 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::H)), Cycles(2.0)), + 0xB5 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::L)), Cycles(2.0)), + 0xB6 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::HL)), Cycles(4.0)), + 0xB7 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I6, Register::A)), Cycles(2.0)), + 0xB8 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::B)), Cycles(2.0)), + 0xB9 => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::C)), Cycles(2.0)), + 0xBA => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::D)), Cycles(2.0)), + 0xBB => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::E)), Cycles(2.0)), + 0xBC => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::H)), Cycles(2.0)), + 0xBD => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::L)), Cycles(2.0)), + 0xBE => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::HL)), Cycles(4.0)), + 0xBF => (Opcode::PrefixCB(CBOpcode::RES(BitIndex::I7, Register::A)), Cycles(2.0)), - 0xC0 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::B)), Cycles(2)), - 0xC1 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::C)), Cycles(2)), - 0xC2 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::D)), Cycles(2)), - 0xC3 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::E)), Cycles(2)), - 0xC4 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::H)), Cycles(2)), - 0xC5 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::L)), Cycles(2)), - 0xC6 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::HL)), Cycles(4)), - 0xC7 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::A)), Cycles(2)), - 0xC8 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::B)), Cycles(2)), - 0xC9 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::C)), Cycles(2)), - 0xCA => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::D)), Cycles(2)), - 0xCB => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::E)), Cycles(2)), - 0xCC => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::H)), Cycles(2)), - 0xCD => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::L)), Cycles(2)), - 0xCE => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::HL)), Cycles(4)), - 0xCF => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::A)), Cycles(2)), - 0xD0 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::B)), Cycles(2)), - 0xD1 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::C)), Cycles(2)), - 0xD2 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::D)), Cycles(2)), - 0xD3 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::E)), Cycles(2)), - 0xD4 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::H)), Cycles(2)), - 0xD5 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::L)), Cycles(2)), - 0xD6 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::HL)), Cycles(4)), - 0xD7 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::A)), Cycles(2)), - 0xD8 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::B)), Cycles(2)), - 0xD9 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::C)), Cycles(2)), - 0xDA => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::D)), Cycles(2)), - 0xDB => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::E)), Cycles(2)), - 0xDC => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::H)), Cycles(2)), - 0xDD => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::L)), Cycles(2)), - 0xDE => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::HL)), Cycles(4)), - 0xDF => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::A)), Cycles(2)), - 0xE0 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::B)), Cycles(2)), - 0xE1 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::C)), Cycles(2)), - 0xE2 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::D)), Cycles(2)), - 0xE3 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::E)), Cycles(2)), - 0xE4 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::H)), Cycles(2)), - 0xE5 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::L)), Cycles(2)), - 0xE6 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::HL)), Cycles(4)), - 0xE7 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::A)), Cycles(2)), - 0xE8 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::B)), Cycles(2)), - 0xE9 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::C)), Cycles(2)), - 0xEA => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::D)), Cycles(2)), - 0xEB => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::E)), Cycles(2)), - 0xEC => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::H)), Cycles(2)), - 0xED => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::L)), Cycles(2)), - 0xEE => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::HL)), Cycles(4)), - 0xEF => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::A)), Cycles(2)), - 0xF0 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::B)), Cycles(2)), - 0xF1 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::C)), Cycles(2)), - 0xF2 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::D)), Cycles(2)), - 0xF3 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::E)), Cycles(2)), - 0xF4 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::H)), Cycles(2)), - 0xF5 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::L)), Cycles(2)), - 0xF6 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::HL)), Cycles(4)), - 0xF7 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::A)), Cycles(2)), - 0xF8 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::B)), Cycles(2)), - 0xF9 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::C)), Cycles(2)), - 0xFA => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::D)), Cycles(2)), - 0xFB => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::E)), Cycles(2)), - 0xFC => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::H)), Cycles(2)), - 0xFD => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::L)), Cycles(2)), - 0xFE => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::HL)), Cycles(4)), - 0xFF => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::A)), Cycles(2)), + 0xC0 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::B)), Cycles(2.0)), + 0xC1 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::C)), Cycles(2.0)), + 0xC2 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::D)), Cycles(2.0)), + 0xC3 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::E)), Cycles(2.0)), + 0xC4 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::H)), Cycles(2.0)), + 0xC5 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::L)), Cycles(2.0)), + 0xC6 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::HL)), Cycles(4.0)), + 0xC7 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I0, Register::A)), Cycles(2.0)), + 0xC8 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::B)), Cycles(2.0)), + 0xC9 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::C)), Cycles(2.0)), + 0xCA => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::D)), Cycles(2.0)), + 0xCB => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::E)), Cycles(2.0)), + 0xCC => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::H)), Cycles(2.0)), + 0xCD => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::L)), Cycles(2.0)), + 0xCE => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::HL)), Cycles(4.0)), + 0xCF => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I1, Register::A)), Cycles(2.0)), + 0xD0 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::B)), Cycles(2.0)), + 0xD1 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::C)), Cycles(2.0)), + 0xD2 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::D)), Cycles(2.0)), + 0xD3 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::E)), Cycles(2.0)), + 0xD4 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::H)), Cycles(2.0)), + 0xD5 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::L)), Cycles(2.0)), + 0xD6 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::HL)), Cycles(4.0)), + 0xD7 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I2, Register::A)), Cycles(2.0)), + 0xD8 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::B)), Cycles(2.0)), + 0xD9 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::C)), Cycles(2.0)), + 0xDA => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::D)), Cycles(2.0)), + 0xDB => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::E)), Cycles(2.0)), + 0xDC => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::H)), Cycles(2.0)), + 0xDD => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::L)), Cycles(2.0)), + 0xDE => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::HL)), Cycles(4.0)), + 0xDF => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I3, Register::A)), Cycles(2.0)), + 0xE0 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::B)), Cycles(2.0)), + 0xE1 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::C)), Cycles(2.0)), + 0xE2 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::D)), Cycles(2.0)), + 0xE3 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::E)), Cycles(2.0)), + 0xE4 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::H)), Cycles(2.0)), + 0xE5 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::L)), Cycles(2.0)), + 0xE6 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::HL)), Cycles(4.0)), + 0xE7 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I4, Register::A)), Cycles(2.0)), + 0xE8 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::B)), Cycles(2.0)), + 0xE9 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::C)), Cycles(2.0)), + 0xEA => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::D)), Cycles(2.0)), + 0xEB => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::E)), Cycles(2.0)), + 0xEC => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::H)), Cycles(2.0)), + 0xED => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::L)), Cycles(2.0)), + 0xEE => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::HL)), Cycles(4.0)), + 0xEF => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I5, Register::A)), Cycles(2.0)), + 0xF0 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::B)), Cycles(2.0)), + 0xF1 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::C)), Cycles(2.0)), + 0xF2 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::D)), Cycles(2.0)), + 0xF3 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::E)), Cycles(2.0)), + 0xF4 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::H)), Cycles(2.0)), + 0xF5 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::L)), Cycles(2.0)), + 0xF6 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::HL)), Cycles(4.0)), + 0xF7 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I6, Register::A)), Cycles(2.0)), + 0xF8 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::B)), Cycles(2.0)), + 0xF9 => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::C)), Cycles(2.0)), + 0xFA => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::D)), Cycles(2.0)), + 0xFB => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::E)), Cycles(2.0)), + 0xFC => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::H)), Cycles(2.0)), + 0xFD => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::L)), Cycles(2.0)), + 0xFE => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::HL)), Cycles(4.0)), + 0xFF => (Opcode::PrefixCB(CBOpcode::SET(BitIndex::I7, Register::A)), Cycles(2.0)), }, - 0xC3 => (Opcode::JP(OpcodeParameter::U16(two_byte_param)), Cycles(4)), - 0xC2 => (Opcode::JP(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), - 0xCA => (Opcode::JP(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), - 0xD2 => (Opcode::JP(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), - 0xDA => (Opcode::JP(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), - 0xE9 => (Opcode::JP(OpcodeParameter::Register(Register::HL)), Cycles(1)), - 0x18 => (Opcode::JR(OpcodeParameter::I8(self.1 as i8)), Cycles(2)), - 0x20 => (Opcode::JR(OpcodeParameter::FlagRegisterReset_I8(FlagRegister::Zero, self.1 as i8)), Cycles(2)), - 0x28 => (Opcode::JR(OpcodeParameter::FlagRegisterSet_I8(FlagRegister::Zero, self.1 as i8)), Cycles(2)), - 0x30 => (Opcode::JR(OpcodeParameter::FlagRegisterReset_I8(FlagRegister::Carry, self.1 as i8)), Cycles(2)), - 0x38 => (Opcode::JR(OpcodeParameter::FlagRegisterSet_I8(FlagRegister::Carry, self.1 as i8)), Cycles(2)), - 0xCD => (Opcode::CALL(OpcodeParameter::U16(two_byte_param)), Cycles(6)), - 0xC4 => (Opcode::CALL(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), - 0xCC => (Opcode::CALL(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Zero, two_byte_param)), Cycles(3)), - 0xD4 => (Opcode::CALL(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), - 0xDC => (Opcode::CALL(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)), - 0xC7 => (Opcode::RST(0x00), Cycles(4)), - 0xCF => (Opcode::RST(0x08), Cycles(4)), - 0xD7 => (Opcode::RST(0x10), Cycles(4)), - 0xDF => (Opcode::RST(0x18), Cycles(4)), - 0xE7 => (Opcode::RST(0x20), Cycles(4)), - 0xEF => (Opcode::RST(0x28), Cycles(4)), - 0xF7 => (Opcode::RST(0x30), Cycles(4)), - 0xFF => (Opcode::RST(0x38), Cycles(4)), - 0xC9 => (Opcode::RET(OpcodeParameter::NoParam), Cycles(4)), - 0xC0 => (Opcode::RET(OpcodeParameter::FlagRegisterReset(FlagRegister::Zero)), Cycles(2)), - 0xC8 => (Opcode::RET(OpcodeParameter::FlagRegisterSet(FlagRegister::Zero)), Cycles(2)), - 0xD0 => (Opcode::RET(OpcodeParameter::FlagRegisterReset(FlagRegister::Carry)), Cycles(2)), - 0xD8 => (Opcode::RET(OpcodeParameter::FlagRegisterSet(FlagRegister::Carry)), Cycles(2)), - 0xD9 => (Opcode::RETI, Cycles(4)), - 0xF3 => (Opcode::DI, Cycles(1)), - 0xFB => (Opcode::EI, Cycles(1)), - 0x76 => (Opcode::HALT, Cycles(1)), - 0x10 => (Opcode::STOP, Cycles(1)), - 0x00 => (Opcode::NOP, Cycles(1)), - _ => (Opcode::IllegalInstruction, Cycles(1)), + 0xC3 => (Opcode::JP(OpcodeParameter::U16(two_byte_param)), Cycles(4.0)), + 0xC2 => (Opcode::JP(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Zero, two_byte_param)), Cycles(3.0)), + 0xCA => (Opcode::JP(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Zero, two_byte_param)), Cycles(3.0)), + 0xD2 => (Opcode::JP(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Carry, two_byte_param)), Cycles(3.0)), + 0xDA => (Opcode::JP(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Carry, two_byte_param)), Cycles(3.0)), + 0xE9 => (Opcode::JP(OpcodeParameter::Register(Register::HL)), Cycles(1.0)), + 0x18 => (Opcode::JR(OpcodeParameter::I8(self.1 as i8)), Cycles(2.0)), + 0x20 => (Opcode::JR(OpcodeParameter::FlagRegisterReset_I8(FlagRegister::Zero, self.1 as i8)), Cycles(2.0)), + 0x28 => (Opcode::JR(OpcodeParameter::FlagRegisterSet_I8(FlagRegister::Zero, self.1 as i8)), Cycles(2.0)), + 0x30 => (Opcode::JR(OpcodeParameter::FlagRegisterReset_I8(FlagRegister::Carry, self.1 as i8)), Cycles(2.0)), + 0x38 => (Opcode::JR(OpcodeParameter::FlagRegisterSet_I8(FlagRegister::Carry, self.1 as i8)), Cycles(2.0)), + 0xCD => (Opcode::CALL(OpcodeParameter::U16(two_byte_param)), Cycles(6.0)), + 0xC4 => (Opcode::CALL(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Zero, two_byte_param)), Cycles(3.0)), + 0xCC => (Opcode::CALL(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Zero, two_byte_param)), Cycles(3.0)), + 0xD4 => (Opcode::CALL(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Carry, two_byte_param)), Cycles(3.0)), + 0xDC => (Opcode::CALL(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Carry, two_byte_param)), Cycles(3.0)), + 0xC7 => (Opcode::RST(0x00), Cycles(4.0)), + 0xCF => (Opcode::RST(0x08), Cycles(4.0)), + 0xD7 => (Opcode::RST(0x10), Cycles(4.0)), + 0xDF => (Opcode::RST(0x18), Cycles(4.0)), + 0xE7 => (Opcode::RST(0x20), Cycles(4.0)), + 0xEF => (Opcode::RST(0x28), Cycles(4.0)), + 0xF7 => (Opcode::RST(0x30), Cycles(4.0)), + 0xFF => (Opcode::RST(0x38), Cycles(4.0)), + 0xC9 => (Opcode::RET(OpcodeParameter::NoParam), Cycles(4.0)), + 0xC0 => (Opcode::RET(OpcodeParameter::FlagRegisterReset(FlagRegister::Zero)), Cycles(2.0)), + 0xC8 => (Opcode::RET(OpcodeParameter::FlagRegisterSet(FlagRegister::Zero)), Cycles(2.0)), + 0xD0 => (Opcode::RET(OpcodeParameter::FlagRegisterReset(FlagRegister::Carry)), Cycles(2.0)), + 0xD8 => (Opcode::RET(OpcodeParameter::FlagRegisterSet(FlagRegister::Carry)), Cycles(2.0)), + 0xD9 => (Opcode::RETI, Cycles(4.0)), + 0xF3 => (Opcode::DI, Cycles(1.0)), + 0xFB => (Opcode::EI, Cycles(1.0)), + 0x76 => (Opcode::HALT, Cycles(1.0)), + 0x10 => (Opcode::STOP, Cycles(1.0)), + 0x00 => (Opcode::NOP, Cycles(1.0)), + _ => (Opcode::IllegalInstruction, Cycles(1.0)), } } } @@ -813,11 +816,11 @@ pub enum CBOpcode { // Store cycles in M #[derive(Debug, Copy, Clone)] -pub struct Cycles(pub usize); +pub struct Cycles(pub f32); impl Cycles { pub fn to_t(&self) -> Self { - Self(self.0 * 4) + Self(self.0 * 4.0) } } @@ -830,32 +833,38 @@ pub struct CPU { ime: bool, // Interrupt Master Enable ei_delay: bool, enable_logs: bool, + is_cgb: bool, + double_speed_mode: bool, } impl CPU { pub fn new() -> Self { Self { registers: Registers::new(), - cycles: Cycles(0), - last_op_cycles: Cycles(0), + cycles: Cycles(0.0), + last_op_cycles: Cycles(0.0), exec_calls_count: 0, is_halted: false, ei_delay: false, ime: true, enable_logs: !env::var("CPU_LOG").is_err() || !env::var("CPU_LOGS").is_err(), + is_cgb: false, + double_speed_mode: false, } } pub fn new_cgb() -> Self { Self { registers: Registers::new_cgb(), - cycles: Cycles(0), - last_op_cycles: Cycles(0), + cycles: Cycles(0.0), + last_op_cycles: Cycles(0.0), exec_calls_count: 0, is_halted: false, ei_delay: false, ime: true, enable_logs: !env::var("CPU_LOG").is_err() || !env::var("CPU_LOGS").is_err(), + is_cgb: true, + double_speed_mode: false, } } @@ -868,11 +877,15 @@ impl CPU { } fn increment_cycles(&mut self, cycles: Cycles) { - self.cycles.0 += cycles.0; + if self.is_cgb && self.double_speed_mode { + self.cycles.0 += cycles.0 / 2.0; + } else { + self.cycles.0 += cycles.0; + } } pub fn reset_cycles(&mut self) { - self.cycles = Cycles(0); + self.cycles = Cycles(0.0); } pub fn get_cycles(&mut self) -> Cycles { @@ -949,7 +962,7 @@ impl CPU { let cycles_start = self.get_cycles(); if let Some(interrupt) = self.check_interrupts(bus) { self.handle_interrupt(bus, interrupt); - self.increment_cycles(Cycles(5)); + self.increment_cycles(Cycles(5.0)); } else if !self.is_halted { let program_counter = self.registers.get(Register::PC); let parameter_bytes = OpcodeParameterBytes::from_address(program_counter, bus); @@ -962,7 +975,7 @@ impl CPU { self.exec(opcode, bus); self.ei_delay(bus); } else if self.is_halted { - self.increment_cycles(Cycles(1)); + self.increment_cycles(Cycles(1.0)); } let cycles_end = self.get_cycles(); self.set_last_op_cycles(cycles_start, cycles_end); @@ -1051,7 +1064,7 @@ impl CPU { _ => unreachable!(), }; if condition_met { - self.increment_cycles(Cycles(1)); + self.increment_cycles(Cycles(1.0)); let pc = (self.registers.get(Register::PC) as i16) + (value as i16); self.registers.set(Register::PC, pc as u16); } @@ -1437,14 +1450,14 @@ impl CPU { self.registers.increment(Register::PC, 3); if !self.registers.get_flag(flag) { self.registers.set(Register::PC, addr); - self.increment_cycles(Cycles(1)); + self.increment_cycles(Cycles(1.0)); } }, OpcodeParameter::FlagRegisterSet_U16(flag, addr) => { self.registers.increment(Register::PC, 3); if self.registers.get_flag(flag) { self.registers.set(Register::PC, addr); - self.increment_cycles(Cycles(1)); + self.increment_cycles(Cycles(1.0)); } }, _ => unreachable!(), @@ -1458,12 +1471,12 @@ impl CPU { }, OpcodeParameter::FlagRegisterReset_U16(flag, address) => { let condition_met = !self.registers.get_flag(flag); - if condition_met {self.increment_cycles(Cycles(3))}; + if condition_met {self.increment_cycles(Cycles(3.0))}; (condition_met, address) }, OpcodeParameter::FlagRegisterSet_U16(flag, address) => { let condition_met = self.registers.get_flag(flag); - if condition_met {self.increment_cycles(Cycles(3))}; + if condition_met {self.increment_cycles(Cycles(3.0))}; (condition_met, address) }, _ => unreachable!(), @@ -1509,13 +1522,13 @@ impl CPU { OpcodeParameter::FlagRegisterReset(flag) => { if !self.registers.get_flag(flag) { self.exec(Opcode::POP(Register::PC), bus); - self.increment_cycles(Cycles(3)); + self.increment_cycles(Cycles(3.0)); } }, OpcodeParameter::FlagRegisterSet(flag) => { if self.registers.get_flag(flag) { self.exec(Opcode::POP(Register::PC), bus); - self.increment_cycles(Cycles(3)); + self.increment_cycles(Cycles(3.0)); } }, _ => unreachable!(), @@ -1783,6 +1796,14 @@ impl CPU { }, Opcode::STOP => { self.registers.increment(Register::PC, 2); + if self.is_cgb && bus.prepare_double_speed_mode() { + bus.set_double_speed_mode(!self.double_speed_mode); + let speed_switch_register = bus.read(PREPARE_SPEED_SWITCH_ADDRESS); + // Disable prepare speed switch + bus.write(PREPARE_SPEED_SWITCH_ADDRESS, speed_switch_register & 0xFE); + println!("Switching speed mode to: {}", !self.double_speed_mode); + self.double_speed_mode = !self.double_speed_mode; + } }, Opcode::NOP => self.registers.increment(Register::PC, 1), Opcode::IllegalInstruction => { diff --git a/src/emulator.rs b/src/emulator.rs index 305c79e..e21d4b7 100644 --- a/src/emulator.rs +++ b/src/emulator.rs @@ -115,8 +115,11 @@ impl Emulator { self.cpu.run(&mut self.bus); let cycles = self.cpu.get_last_op_cycles().to_t(); self.bus.ppu.do_cycles(&mut self.bus.interrupts, cycles, frame_buffer); - self.bus.timer.do_cycles(&mut self.bus.interrupts, cycles); self.bus.sound.do_cycles(cycles); + self.bus.timer.do_cycles(&mut self.bus.interrupts, cycles); + if self.bus.double_speed_mode() { + self.bus.timer.do_cycles(&mut self.bus.interrupts, Cycles(cycles.0 * 3.0)); + } // 1 CPU cycle = 238.42ns // thread::sleep(time::Duration::from_nanos((self.cpu.get_last_op_cycles().0 * 238).try_into().unwrap())); diff --git a/src/ppu.rs b/src/ppu.rs index 8976b2f..8677b33 100644 --- a/src/ppu.rs +++ b/src/ppu.rs @@ -316,7 +316,7 @@ impl PPU { window_enable: false, window_drawn: false, lcd_enable: false, - cycles: Cycles(0), + cycles: Cycles(0.0), sprite_buffer: Vec::new(), window_y_counter: 0, last_bg_index: 0, @@ -482,7 +482,7 @@ impl PPU { } pub fn reset_cycles(&mut self) { - self.cycles.0 = 0; + self.cycles.0 = 0.0; } pub fn increment_cycles(&mut self, cycles: Cycles) { @@ -496,19 +496,19 @@ impl PPU { } if self.lcd_y < 144 { - if self.cycles.0 <= 80 && !self.get_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::SearchingOAM)) { + if self.cycles.0 <= 80.0 && !self.get_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::SearchingOAM)) { // Mode 2 OAM scan self.set_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::SearchingOAM), true); self.stat_interrupt(interrupts); self.oam_search(); - } else if self.cycles.0 > 80 && self.cycles.0 <= 80 + 172 { + } else if self.cycles.0 > 80.0 && self.cycles.0 <= 80.0 + 172.0 { // Mode 3 drawing pixel line. This could also last 289 cycles if !self.get_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::TransferringToLCD)) { self.window_drawn = false; self.set_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::TransferringToLCD), true); } self.draw_line(cycles, frame_buffer); - } else if self.cycles.0 > 80 + 172 && self.cycles.0 <= 80 + 172 + 204 && !self.get_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::HBlank)) { + } else if self.cycles.0 > 80.0 + 172.0 && self.cycles.0 <= 80.0 + 172.0 + 204.0 && !self.get_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::HBlank)) { // Mode 0 Horizontal blank. This could last 87 or 204 cycles depending on the mode 3 self.set_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::HBlank), true); self.stat_interrupt(interrupts); @@ -523,7 +523,7 @@ impl PPU { self.increment_cycles(cycles); // Horizontal scan completed - if self.cycles.0 > 456 { + if self.cycles.0 > 456.0 { self.reset_cycles(); self.lcd_y = self.lcd_y.wrapping_add(1); @@ -855,7 +855,7 @@ impl PPU { self.current_background_pixels = None; self.current_window_pixels = None; self.bg_palette = self.get_register(BACKGROUND_PALETTE_ADDRESS); - let mut count = 0; + let mut count = 0.0; while count < cycles.0 && (self.lcd_x as u32) < LCD_WIDTH { let idx = (self.lcd_x as usize + (self.lcd_y as usize * LCD_WIDTH as usize)) * 4; @@ -896,7 +896,7 @@ impl PPU { } self.lcd_x += 1; - count += 1; + count += 1.0; } } diff --git a/src/render.rs b/src/render.rs index 642b053..f2e640c 100644 --- a/src/render.rs +++ b/src/render.rs @@ -81,7 +81,7 @@ pub fn start_eventloop() { *control_flow = ControlFlow::Exit }, Event::MainEventsCleared => { - emulator.run(Cycles(70224), pixels.get_frame()); + emulator.run(Cycles(70224.0), pixels.get_frame()); frame_counter.increment(); if frame_counter.elapsed_ms() >= 1000 { window.set_title(&format!("rmg-001 (FPS: {})", frame_counter.count())); diff --git a/src/sound.rs b/src/sound.rs index a219adc..6cf72ca 100644 --- a/src/sound.rs +++ b/src/sound.rs @@ -175,10 +175,10 @@ impl Sound { } pub fn do_cycles(&mut self, cycles: Cycles) { - let mut count = 0; + let mut count = 0.0; while count < cycles.0 { self.cycle(); - count += 1; + count += 1.0; } } diff --git a/src/timer.rs b/src/timer.rs index e5b29a2..b1cbe4d 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -68,10 +68,10 @@ impl Timer { pub fn do_cycles(&mut self, interrupts: &mut Interrupts, cycles: Cycles) { self.is_enabled = self.is_timer_enabled(); self.control = self.get_register(TIMER_CONTROL_ADDRESS); - let mut count = 0; + let mut count = 0.0; while count < cycles.0 { self.cycle(interrupts); - count += 1; + count += 1.0; } } @@ -120,18 +120,18 @@ mod tests { timer.set_register(TIMER_CONTROL_ADDRESS, 0b101); timer.set_register(TIMER_COUNTER_ADDRESS, 0); timer.set_div(0b10111); - timer.do_cycles(&mut interrupts, Cycles(1)); + timer.do_cycles(&mut interrupts, Cycles(1.0)); assert_eq!(timer.div(), 0b11000); assert_eq!(timer.prev_result(), true); assert_eq!(timer.get_register(TIMER_COUNTER_ADDRESS), 0); assert_eq!(interrupts.get(Interrupt::Timer), false); - timer.do_cycles(&mut interrupts, Cycles(7)); + timer.do_cycles(&mut interrupts, Cycles(7.0)); assert_eq!(timer.div(), 0b11111); assert_eq!(timer.prev_result(), true); assert_eq!(timer.get_register(TIMER_COUNTER_ADDRESS), 0); assert_eq!(interrupts.get(Interrupt::Timer), false); - timer.do_cycles(&mut interrupts, Cycles(1)); + timer.do_cycles(&mut interrupts, Cycles(1.0)); assert_eq!(timer.div(), 0b100000); assert_eq!(timer.get_register(TIMER_COUNTER_ADDRESS), 1); assert_eq!(timer.prev_result(), false); @@ -145,7 +145,7 @@ mod tests { timer.set_register(TIMER_CONTROL_ADDRESS, 0b101); timer.set_register(TIMER_COUNTER_ADDRESS, 0xFF); timer.set_div(0b10111); - timer.do_cycles(&mut interrupts, Cycles(9)); + timer.do_cycles(&mut interrupts, Cycles(9.0)); assert_eq!(timer.div(), 0b100000); assert_eq!(timer.get_register(TIMER_COUNTER_ADDRESS), 0x00); assert_eq!(interrupts.get(Interrupt::Timer), true); @@ -158,11 +158,11 @@ mod tests { timer.set_register(TIMER_CONTROL_ADDRESS, 0b101); timer.set_register(TIMER_COUNTER_ADDRESS, 0); timer.set_div(0b11000); - timer.do_cycles(&mut interrupts, Cycles(1)); + timer.do_cycles(&mut interrupts, Cycles(1.0)); assert_eq!(timer.div(), 0b11001); assert_eq!(timer.get_register(TIMER_COUNTER_ADDRESS), 0); timer.set_register(TIMER_CONTROL_ADDRESS, 0b001); - timer.do_cycles(&mut interrupts, Cycles(1)); + timer.do_cycles(&mut interrupts, Cycles(1.0)); assert_eq!(timer.div(), 0b11010); assert_eq!(timer.get_register(TIMER_COUNTER_ADDRESS), 1); }