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more CALL instructions
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parent
31e0b2c79c
commit
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62
src/cpu.rs
62
src/cpu.rs
@ -537,16 +537,30 @@ impl CPU {
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// CALL
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// CALL
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Opcode::CALL(params) => {
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Opcode::CALL(params) => {
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self.registers.increment(Register::PC, 3);
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self.registers.increment(Register::PC, 3);
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let mut condition_met = false;
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let mut addr = self.registers.get(Register::PC);
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match params {
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match params {
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OpcodeParameter::U16(address) => {
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OpcodeParameter::U16(address) => {
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let pc = self.registers.get(Register::PC);
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condition_met = true;
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self.registers.decrement(Register::SP, 2);
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addr = address;
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let sp = self.registers.get(Register::SP);
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},
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bus.write_16bit(sp, pc);
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OpcodeParameter::FlagRegisterReset_U16(flag, address) => {
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self.registers.set(Register::PC, address);
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condition_met = !self.registers.get_flag(flag);
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addr = address;
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},
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OpcodeParameter::FlagRegisterSet_U16(flag, address) => {
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condition_met = self.registers.get_flag(flag);
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addr = address;
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},
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},
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_ => {},
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_ => {},
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};
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};
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if condition_met {
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let pc = self.registers.get(Register::PC);
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self.registers.decrement(Register::SP, 2);
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let sp = self.registers.get(Register::SP);
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bus.write_16bit(sp, pc);
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self.registers.set(Register::PC, addr);
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}
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},
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},
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// RST, same as Call
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// RST, same as Call
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Opcode::RST(address) => self.exec(Opcode::CALL(OpcodeParameter::U16(address as u16)), bus),
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Opcode::RST(address) => self.exec(Opcode::CALL(OpcodeParameter::U16(address as u16)), bus),
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@ -1111,6 +1125,44 @@ mod tests {
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assert_eq!(cpu.registers.get(Register::SP), sp - 2);
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assert_eq!(cpu.registers.get(Register::SP), sp - 2);
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assert_eq!(cpu.registers.get(Register::PC), 0xF0F0);
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assert_eq!(cpu.registers.get(Register::PC), 0xF0F0);
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let mut cpu = CPU::new();
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let sp = 0xFFDF;
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cpu.registers.set(Register::SP, sp);
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cpu.registers.set_flag(FlagRegister::Zero, false);
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cpu.registers.set(Register::PC, 0x1234);
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cpu.exec(Opcode::CALL(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Zero, 0xF0F0)), &mut bus);
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assert_eq!(bus.read_16bit(sp - 2), 0x1234 + 3);
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assert_eq!(cpu.registers.get(Register::SP), sp - 2);
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assert_eq!(cpu.registers.get(Register::PC), 0xF0F0);
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let mut cpu = CPU::new();
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let sp = 0xFFDF;
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cpu.registers.set(Register::SP, sp);
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cpu.registers.set_flag(FlagRegister::Zero, true);
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cpu.exec(Opcode::CALL(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Zero, 0xF0F0)), &mut bus);
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// assert_eq!(bus.read_16bit(sp - 2), 0x1234 + 3);
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assert_eq!(cpu.registers.get(Register::SP), sp);
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assert_eq!(cpu.registers.get(Register::PC), 0x103);
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let mut cpu = CPU::new();
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let sp = 0xFFDF;
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cpu.registers.set(Register::SP, sp);
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cpu.registers.set_flag(FlagRegister::Zero, true);
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cpu.registers.set(Register::PC, 0x1234);
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cpu.exec(Opcode::CALL(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Zero, 0xF0F0)), &mut bus);
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assert_eq!(bus.read_16bit(sp - 2), 0x1234 + 3);
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assert_eq!(cpu.registers.get(Register::SP), sp - 2);
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assert_eq!(cpu.registers.get(Register::PC), 0xF0F0);
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let mut cpu = CPU::new();
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let sp = 0xFFDF;
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cpu.registers.set(Register::SP, sp);
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cpu.registers.set_flag(FlagRegister::Zero, false);
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cpu.exec(Opcode::CALL(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Zero, 0xF0F0)), &mut bus);
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// assert_eq!(bus.read_16bit(sp - 2), 0x1234 + 3);
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assert_eq!(cpu.registers.get(Register::SP), sp);
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assert_eq!(cpu.registers.get(Register::PC), 0x103);
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// RST
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// RST
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let mut cpu = CPU::new();
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let mut cpu = CPU::new();
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let sp = 0xFFDF;
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let sp = 0xFFDF;
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