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Fix INC and DEC

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This commit is contained in:
Franco Colmenarez 2021-10-18 17:27:46 -05:00
parent 199470cc70
commit ac91f8f50d
1 changed files with 36 additions and 24 deletions
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56
src/cpu.rs
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@ -639,37 +639,45 @@ impl CPU {
},
// Increment by 1
Opcode::INC(affect_flags, register) => {
let prev_value = self.registers.get(register);
self.registers.increment(Register::PC, 1);
let mut prev_value = 0;
let mut result = 0;
if register.is_8bit() {
prev_value = self.registers.get_8bit(register);
self.registers.increment(register, 1);
result = self.registers.get_8bit(register);
} else {
let addr = self.registers.get(register);
prev_value = bus.read(addr);
bus.write(addr, prev_value + 1);
result = bus.read(addr);
}
if affect_flags {
self.registers.set_flag(FlagRegister::Substract, false);
let mut byte_compare = 0;
match register.is_8bit() {
true => byte_compare = prev_value.to_be_bytes()[1],
false => byte_compare = prev_value.to_be_bytes()[0],
}
self.registers.set_flag(FlagRegister::HalfCarry, add_half_carry(byte_compare, 1));
let result = self.registers.get(register);
self.registers.set_flag(FlagRegister::HalfCarry, add_half_carry(prev_value, 1));
self.registers.set_flag(FlagRegister::Zero, result == 0);
}
self.registers.increment(Register::PC, 1);
},
// Decrement by 1
Opcode::DEC(affect_flags, register) => {
let prev_value = self.registers.get(register);
self.registers.increment(Register::PC, 1);
let mut prev_value = 0;
let mut result = 0;
if register.is_8bit() {
prev_value = self.registers.get_8bit(register);
self.registers.decrement(register, 1);
result = self.registers.get_8bit(register);
} else {
let addr = self.registers.get(register);
prev_value = bus.read(addr);
bus.write(addr, prev_value - 1);
result = bus.read(addr);
}
if affect_flags {
self.registers.set_flag(FlagRegister::Substract, true);
let mut byte_compare = 0;
match register.is_8bit() {
true => byte_compare = prev_value.to_be_bytes()[1],
false => byte_compare = prev_value.to_be_bytes()[0],
}
self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(byte_compare, 1));
let result = self.registers.get(register);
self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(prev_value, 1));
self.registers.set_flag(FlagRegister::Zero, result == 0);
}
self.registers.increment(Register::PC, 1);
},
// Jump to address
Opcode::JP(params) => match params {
@ -2335,12 +2343,14 @@ mod tests {
assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
assert_eq!(cpu.registers.get(Register::PC), 0x101);
let mut cpu = CPU::new();
cpu.registers.set(Register::HL, 0b0000111111111111);
let addr = 0xC000;
cpu.registers.set(Register::HL, addr);
bus.write(addr, 0b00001111);
cpu.exec(Opcode::INC(true, Register::HL), &mut bus);
assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
assert_eq!(cpu.registers.get(Register::HL), 0b0001000000000000);
assert_eq!(bus.read(addr), 0b00010000);
assert_eq!(cpu.registers.get(Register::PC), 0x101);
}
@ -2364,12 +2374,14 @@ mod tests {
assert_eq!(cpu.registers.get(Register::A), 0b00001111);
assert_eq!(cpu.registers.get(Register::PC), 0x101);
let mut cpu = CPU::new();
cpu.registers.set(Register::HL, 0b0001000000000000);
let addr = 0xC000;
cpu.registers.set(Register::HL, addr);
bus.write(addr, 0b00010000);
cpu.exec(Opcode::DEC(true, Register::HL), &mut bus);
assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), true);
assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
assert_eq!(cpu.registers.get(Register::HL), 0b0000111111111111);
assert_eq!(bus.read(addr), 0b00001111);
assert_eq!(cpu.registers.get(Register::PC), 0x101);
}