diff --git a/src/bin/main.rs b/src/bin/main.rs
index 5edfbfa..d36f898 100644
--- a/src/bin/main.rs
+++ b/src/bin/main.rs
@@ -2,7 +2,9 @@ use rust_boy::rom::ROM;
 use rust_boy::console::Console;
 
 fn main() -> std::io::Result<()> {
-    let mut console = Console::new();
-    console.cpu_run();
+    /* let mut console = Console::new();
+    console.cpu_run(); */
+    let val: u8 = 0b11110000;
+    println!("{:08b}", !val);
     Ok(())
 }
diff --git a/src/cpu.rs b/src/cpu.rs
index 6c58f5d..909ba14 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -222,7 +222,7 @@ pub enum Opcode {
     LD(OpcodeParameter),
     LDD(OpcodeParameter),
     LDI(OpcodeParameter),
-    LDHL(OpcodeParameter),
+    // LDHL(OpcodeParameter),
     PUSH(Register),
     POP(Register),
     ADD(OpcodeParameter),
@@ -1025,6 +1025,12 @@ impl CPU {
                     _ => {},
                 };
             },
+            Opcode::CPL => {
+                self.registers.increment(Register::PC, 1);
+                self.registers.set(Register::A, !self.registers.get(Register::A));
+                self.registers.set_flag(FlagRegister::Substract, true);
+                self.registers.set_flag(FlagRegister::HalfCarry, true);
+            },
             // Disable interrupts
             Opcode::DI => {
                 bus.write(0xFFFF, 0x00); // Disable all interrupts
@@ -2987,6 +2993,18 @@ mod tests {
         assert_eq!(cpu.registers.get(Register::PC), 0x101);
     }
 
+    #[test]
+    fn test_cpl_instructions() {
+        let mut cpu = CPU::new();
+        let mut bus = Bus::new();
+        cpu.registers.set(Register::A, 0b11110000);
+        cpu.exec(Opcode::CPL, &mut bus);
+        assert_eq!(cpu.registers.get(Register::A), 0b00001111);
+        assert_eq!(cpu.registers.get(Register::PC), 0x101);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), true);
+        assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
+    }
+
     #[test]
     fn test_nop_instructions() {
         let mut cpu = CPU::new();