From aded5fe5340e926f6308b1c27c00bed6248f57f8 Mon Sep 17 00:00:00 2001
From: Franco Colmenarez <info@francoacg.com>
Date: Mon, 18 Oct 2021 13:15:26 -0500
Subject: [PATCH] ADC and SBC instructions (no tests)

---
 src/cpu.rs   | 42 ++++++++++++++++++++++++++++++++++++++++++
 src/utils.rs |  2 +-
 2 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/src/cpu.rs b/src/cpu.rs
index 79d0705..eded4dd 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -561,6 +561,27 @@ impl CPU {
                     _ => {},
                 };
             },
+            Opcode::ADC(params) => match params {
+                OpcodeParameter::Register_Register(reg1, reg2) => {
+                    if self.registers.get_flag(FlagRegister::Carry) {
+                        self.registers.increment(reg1, 1);
+                    }
+                    self.exec(Opcode::ADD(OpcodeParameter::Register_Register(reg1, reg2)), bus);
+                },
+                OpcodeParameter::Register_U8(reg1, val) => {
+                    if self.registers.get_flag(FlagRegister::Carry) {
+                        self.registers.increment(reg1, 1);
+                    }
+                    self.exec(Opcode::ADD(OpcodeParameter::Register_U8(reg1, val)), bus);
+                },
+                OpcodeParameter::Register_I8(reg1, val) => {
+                    if self.registers.get_flag(FlagRegister::Carry) {
+                        self.registers.increment(reg1, 1);
+                    }
+                    self.exec(Opcode::ADD(OpcodeParameter::Register_I8(reg1, val)), bus);
+                },
+                _ => {},
+            },
             Opcode::SUB(params) => {
                 self.registers.increment(Register::PC, 1);
                 let mut register = Register::A;
@@ -595,6 +616,27 @@ impl CPU {
                 self.registers.set_flag(FlagRegister::Carry, carry);
                 self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(val1.to_be_bytes()[1], val2.to_be_bytes()[1]));
             },
+            Opcode::SBC(params) => match params {
+                OpcodeParameter::Register_Register(reg1, reg2) => {
+                    if self.registers.get_flag(FlagRegister::Carry) {
+                        self.registers.decrement(reg1, 1);
+                    }
+                    self.exec(Opcode::SUB(OpcodeParameter::Register_Register(reg1, reg2)), bus);
+                },
+                OpcodeParameter::Register_U8(reg1, val) => {
+                    if self.registers.get_flag(FlagRegister::Carry) {
+                        self.registers.decrement(reg1, 1);
+                    }
+                    self.exec(Opcode::SUB(OpcodeParameter::Register_U8(reg1, val)), bus);
+                },
+                OpcodeParameter::Register_I8(reg1, val) => {
+                    if self.registers.get_flag(FlagRegister::Carry) {
+                        self.registers.decrement(reg1, 1);
+                    }
+                    self.exec(Opcode::SUB(OpcodeParameter::Register_I8(reg1, val)), bus);
+                },
+                _ => {},
+            },
             // Increment by 1
             Opcode::INC(affect_flags, register) => {
                 let prev_value = self.registers.get(register);
diff --git a/src/utils.rs b/src/utils.rs
index 7fcdee8..8a8927a 100644
--- a/src/utils.rs
+++ b/src/utils.rs
@@ -1,4 +1,4 @@
-#[derive(Debug)]
+#[derive(Debug, Copy, Clone)]
 pub enum BitIndex {
     I0,
     I1,