mirror of
https://github.com/FranLMSP/rmg-001.git
synced 2024-11-23 10:12:11 +00:00
Fix some tests, add a couple of new instructions and fix LD instruction bug
This commit is contained in:
parent
9d8d05c660
commit
afaecf597f
96
src/cpu.rs
96
src/cpu.rs
@ -296,10 +296,27 @@ impl CPU {
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match opcode {
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// Load
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Opcode::LD(params) => match params {
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OpcodeParameter::Register_Register(reg1, reg2) => {
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if reg1.is_16bit() && reg2.is_8bit() {
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let val = self.registers.get(reg2).to_be_bytes()[1];
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let addr = self.registers.get(reg1);
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bus.write(addr, val);
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} else if reg1.is_8bit() && reg2.is_16bit() {
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let val = bus.read(self.registers.get(reg2)) as u16;
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self.registers.set(reg1, val);
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} else {
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self.registers.set(reg1, self.registers.get(reg2));
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}
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self.registers.increment(Register::PC, 1);
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},
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OpcodeParameter::Register_U16(register, val) => {
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self.registers.set(register, val);
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self.registers.increment(Register::PC, 3);
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},
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OpcodeParameter::Register_U8(register, val) => {
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self.registers.set(register, val as u16);
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self.registers.increment(Register::PC, 2);
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},
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OpcodeParameter::U16_Register(address, register) => {
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let value = self.registers.get(register);
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let bytes = value.to_be_bytes();
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@ -310,7 +327,17 @@ impl CPU {
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self.registers.increment(Register::PC, 3);
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},
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_ => {},
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}
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},
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// Load and increment
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Opcode::LDI(params) => match params {
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OpcodeParameter::Register_RegisterIncrement(reg1, reg2) => {
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let val = bus.read(self.registers.get(reg2));
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self.registers.set(reg1, val as u16);
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self.registers.increment(reg2, 1);
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self.registers.increment(Register::PC, 1);
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},
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_ => {},
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},
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// Increment by 1
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Opcode::INC(affect_flags, register) => {
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let prev_value = self.registers.get(register);
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@ -381,12 +408,10 @@ impl CPU {
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}
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},
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// RET, same as POP PC when no parameter is specified
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Opcode::RET(params) => {
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match params {
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Opcode::RET(params) => match params {
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OpcodeParameter::NoParam => self.exec(Opcode::POP(Register::PC), bus),
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_ => {},
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}
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}
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// Rotate A Left
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Opcode::RLCA => {
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let val = self.registers.get(Register::A).to_be_bytes()[1];
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@ -749,11 +774,25 @@ mod tests {
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#[test]
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fn test_cpu_instructions() {
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// LD
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let mut bus = Bus::new();
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0xFF);
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cpu.exec(Opcode::LD(OpcodeParameter::Register_Register(Register::B, Register::A)), &mut bus);
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assert_eq!(cpu.registers.get(Register::B), 0xFF);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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cpu.exec(Opcode::LD(OpcodeParameter::Register_U16(Register::SP, 0xF1F1)), &mut bus);
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assert_eq!(cpu.registers.get(Register::SP), 0xF1F1);
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assert_eq!(cpu.registers.get(Register::PC), 0x103);
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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cpu.exec(Opcode::LD(OpcodeParameter::Register_U8(Register::B, 0xF1)), &mut bus);
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assert_eq!(cpu.registers.get(Register::B), 0xF1);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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cpu.registers.set(Register::SP, 0x1234);
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@ -761,6 +800,39 @@ mod tests {
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assert_eq!(bus.read_16bit(0xF0F0), 0x1234);
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assert_eq!(cpu.registers.get(Register::PC), 0x103);
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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let addr = 0xC000;
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cpu.registers.set(Register::A, 0xFF);
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cpu.registers.set(Register::HL, addr);
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bus.write(addr, 0x00);
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cpu.exec(Opcode::LD(OpcodeParameter::Register_Register(Register::HL, Register::A)), &mut bus);
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assert_eq!(bus.read(addr), 0xFF);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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let addr = 0xC000;
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cpu.registers.set(Register::A, 0x00);
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cpu.registers.set(Register::HL, addr);
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bus.write(addr, 0xFF);
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cpu.exec(Opcode::LD(OpcodeParameter::Register_Register(Register::A, Register::HL)), &mut bus);
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assert_eq!(cpu.registers.get(Register::A), 0xFF);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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// LDI
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let mut bus = Bus::new();
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let mut cpu = CPU::new();
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let addr = 0xC000;
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cpu.registers.set(Register::A, 0x00);
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cpu.registers.set(Register::HL, addr);
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bus.write(addr, 0xF1);
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cpu.exec(Opcode::LDI(OpcodeParameter::Register_RegisterIncrement(Register::A, Register::HL)), &mut bus);
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assert_eq!(bus.read(addr), 0xF1);
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assert_eq!(cpu.registers.get(Register::A), 0xF1);
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assert_eq!(cpu.registers.get(Register::HL), addr + 1);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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// JP
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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@ -777,12 +849,14 @@ mod tests {
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// RLCA
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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cpu.registers.set_flag(FlagRegister::Carry, false);
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cpu.registers.set(Register::A, 0b00000010);
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cpu.exec(Opcode::RLCA, &mut bus);
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assert_eq!(cpu.registers.get(Register::A), 0b00000010);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set_flag(FlagRegister::Carry, false);
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cpu.registers.set(Register::A, 0b00000001);
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cpu.exec(Opcode::RLCA, &mut bus);
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assert_eq!(cpu.registers.get(Register::A), 0b00000001);
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@ -792,11 +866,13 @@ mod tests {
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// RRCA
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0b01000000);
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cpu.registers.set_flag(FlagRegister::Carry, false);
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cpu.exec(Opcode::RRCA, &mut bus);
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assert_eq!(cpu.registers.get(Register::A), 0b01000000);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set_flag(FlagRegister::Carry, false);
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cpu.registers.set(Register::A, 0b10000000);
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cpu.exec(Opcode::RRCA, &mut bus);
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assert_eq!(cpu.registers.get(Register::A), 0b10000000);
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@ -844,12 +920,16 @@ mod tests {
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// INC
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0);
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cpu.registers.set_flag(FlagRegister::Zero, false);
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cpu.registers.set_flag(FlagRegister::HalfCarry, false);
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cpu.exec(Opcode::INC(true, Register::A), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set_flag(FlagRegister::Zero, false);
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cpu.registers.set_flag(FlagRegister::HalfCarry, false);
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cpu.registers.set(Register::A, 0b00001111);
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cpu.exec(Opcode::INC(true, Register::A), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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@ -857,6 +937,8 @@ mod tests {
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set_flag(FlagRegister::Zero, false);
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cpu.registers.set_flag(FlagRegister::HalfCarry, false);
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cpu.registers.set(Register::HL, 0b0000111111111111);
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cpu.exec(Opcode::INC(true, Register::HL), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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@ -867,6 +949,8 @@ mod tests {
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// DEC
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let mut cpu = CPU::new();
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cpu.registers.set_flag(FlagRegister::Carry, false);
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cpu.registers.set_flag(FlagRegister::HalfCarry, false);
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cpu.registers.set(Register::A, 1);
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cpu.exec(Opcode::DEC(true, Register::A), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
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@ -875,6 +959,8 @@ mod tests {
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assert_eq!(cpu.registers.get(Register::A), 0);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set_flag(FlagRegister::Zero, false);
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cpu.registers.set_flag(FlagRegister::Carry, false);
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cpu.registers.set(Register::A, 0b00010000);
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cpu.exec(Opcode::DEC(true, Register::A), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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@ -883,6 +969,8 @@ mod tests {
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assert_eq!(cpu.registers.get(Register::A), 0b00001111);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set_flag(FlagRegister::Zero, false);
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cpu.registers.set_flag(FlagRegister::Carry, false);
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cpu.registers.set(Register::HL, 0b0001000000000000);
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cpu.exec(Opcode::DEC(true, Register::HL), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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