From b6b7e7bf7340371db9add1a3f205a1a7430e53d6 Mon Sep 17 00:00:00 2001
From: Franco Colmenarez <info@francoacg.com>
Date: Tue, 19 Oct 2021 10:41:18 -0500
Subject: [PATCH] Last interrupt instructions

---
 src/cpu.rs | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/cpu.rs b/src/cpu.rs
index ad5db8e..2d6b754 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -222,7 +222,7 @@ pub enum Opcode {
     LD(OpcodeParameter),
     LDD(OpcodeParameter),
     LDI(OpcodeParameter),
-    // LDHL(OpcodeParameter),
+    LDHL(OpcodeParameter),
     PUSH(Register),
     POP(Register),
     ADD(OpcodeParameter),
@@ -1045,11 +1045,28 @@ impl CPU {
                 self.registers.set_flag(FlagRegister::Substract, false);
                 self.registers.set_flag(FlagRegister::HalfCarry, false);
             },
+            // Enable interrupts
+            Opcode::EI => {
+                self.registers.increment(Register::PC, 1);
+                bus.write(0xFFFF, 0xFF); // Disable all interrupts
+            },
             // Disable interrupts
             Opcode::DI => {
                 self.registers.increment(Register::PC, 1);
                 bus.write(0xFFFF, 0x00); // Disable all interrupts
             },
+            // Same as enabling interrupts and then executing RET
+            Opcode::RETI => {
+                self.exec(Opcode::EI, bus);
+                self.exec(Opcode::RET(OpcodeParameter::NoParam), bus);
+            },
+            // WIP
+            Opcode::HALT => {
+                self.registers.increment(Register::PC, 1);
+            },
+            Opcode::STOP => {
+                self.registers.increment(Register::PC, 2);
+            },
             Opcode::NOP => self.registers.increment(Register::PC, 1),
             // _ => println!("Illegal instruction"),
             _ => {},