FranLMSP/rmg-001
1
0
Fork 0
mirror of https://github.com/FranLMSP/rmg-001.git synced 2024-09-20 10:10:50 +00:00
Code Issues Projects Releases Wiki Activity

Mapping opcodes

Browse Source
This commit is contained in:
Franco Colmenarez 2021-10-11 20:38:37 -05:00
parent 5e825a9298
commit bbf6b19957
1 changed files with 311 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

311
src/cpu.rs
View File

@ -139,10 +139,321 @@ impl Registers {
}
}
pub enum CpuOpcode {
LD,
LDD,
LDI,
LDHL,
PUSH,
POP,
ADC,
SUB,
SBC,
AND,
OR,
XOR,
CP,
ADD,
INC,
DEC,
SWAP,
DAA,
CPL,
CCF,
SCF,
NOP,
HALT,
STOP,
DI,
EI,
RLCA,
RLA,
RRCA,
RRA,
RLC,
RL,
RRC,
RR,
SLA,
SRA,
SRL,
BIT,
SET,
RES,
JP,
JR,
CALL,
RST,
RET,
RETI,
}
pub struct CPU {
registers: Registers,
}
impl CPU {
pub fn parse_opcode(opcode: u8) -> CpuOpcode {
match opcode {
0x06 => CpuOpcode::LD,
0x0E => CpuOpcode::LD,
0x16 => CpuOpcode::LD,
0x1E => CpuOpcode::LD,
0x26 => CpuOpcode::LD,
0x2E => CpuOpcode::LD,
0x7F => CpuOpcode::LD,
0x78 => CpuOpcode::LD,
0x79 => CpuOpcode::LD,
0x7A => CpuOpcode::LD,
0x7B => CpuOpcode::LD,
0x7C => CpuOpcode::LD,
0x7D => CpuOpcode::LD,
0x7E => CpuOpcode::LD,
0x40 => CpuOpcode::LD,
0x41 => CpuOpcode::LD,
0x42 => CpuOpcode::LD,
0x43 => CpuOpcode::LD,
0x44 => CpuOpcode::LD,
0x45 => CpuOpcode::LD,
0x46 => CpuOpcode::LD,
0x48 => CpuOpcode::LD,
0x49 => CpuOpcode::LD,
0x4A => CpuOpcode::LD,
0x4B => CpuOpcode::LD,
0x4C => CpuOpcode::LD,
0x4D => CpuOpcode::LD,
0x4E => CpuOpcode::LD,
0x50 => CpuOpcode::LD,
0x51 => CpuOpcode::LD,
0x52 => CpuOpcode::LD,
0x53 => CpuOpcode::LD,
0x54 => CpuOpcode::LD,
0x55 => CpuOpcode::LD,
0x56 => CpuOpcode::LD,
0x58 => CpuOpcode::LD,
0x59 => CpuOpcode::LD,
0x5A => CpuOpcode::LD,
0x5B => CpuOpcode::LD,
0x5C => CpuOpcode::LD,
0x5D => CpuOpcode::LD,
0x5E => CpuOpcode::LD,
0x60 => CpuOpcode::LD,
0x61 => CpuOpcode::LD,
0x62 => CpuOpcode::LD,
0x63 => CpuOpcode::LD,
0x64 => CpuOpcode::LD,
0x65 => CpuOpcode::LD,
0x66 => CpuOpcode::LD,
0x68 => CpuOpcode::LD,
0x69 => CpuOpcode::LD,
0x6A => CpuOpcode::LD,
0x6B => CpuOpcode::LD,
0x6C => CpuOpcode::LD,
0x6D => CpuOpcode::LD,
0x6E => CpuOpcode::LD,
0x70 => CpuOpcode::LD,
0x71 => CpuOpcode::LD,
0x72 => CpuOpcode::LD,
0x73 => CpuOpcode::LD,
0x74 => CpuOpcode::LD,
0x75 => CpuOpcode::LD,
0x36 => CpuOpcode::LD,
0x0A => CpuOpcode::LD,
0x1A => CpuOpcode::LD,
0xFA => CpuOpcode::LD,
0x3E => CpuOpcode::LD,
0x47 => CpuOpcode::LD,
0x4F => CpuOpcode::LD,
0x57 => CpuOpcode::LD,
0x5F => CpuOpcode::LD,
0x67 => CpuOpcode::LD,
0x6F => CpuOpcode::LD,
0x02 => CpuOpcode::LD,
0x12 => CpuOpcode::LD,
0x77 => CpuOpcode::LD,
0xEA => CpuOpcode::LD,
0xF2 => CpuOpcode::LD,
0xE2 => CpuOpcode::LD,
0x3A => CpuOpcode::LD,
0x32 => CpuOpcode::LDD,
0x2A => CpuOpcode::LDI,
0x22 => CpuOpcode::LDI,
0xE0 => CpuOpcode::LD,
0xF0 => CpuOpcode::LD,
0x01 => CpuOpcode::LD,
0x11 => CpuOpcode::LD,
0x21 => CpuOpcode::LD,
0x31 => CpuOpcode::LD,
0xF9 => CpuOpcode::LD,
0xF8 => CpuOpcode::LDHL,
0x08 => CpuOpcode::LD,
0xF5 => CpuOpcode::PUSH,
0xC5 => CpuOpcode::PUSH,
0xD5 => CpuOpcode::PUSH,
0xE5 => CpuOpcode::PUSH,
0xF1 => CpuOpcode::POP,
0xC1 => CpuOpcode::POP,
0xD1 => CpuOpcode::POP,
0xE1 => CpuOpcode::POP,
0x87 => CpuOpcode::ADD,
0x80 => CpuOpcode::ADD,
0x81 => CpuOpcode::ADD,
0x82 => CpuOpcode::ADD,
0x83 => CpuOpcode::ADD,
0x84 => CpuOpcode::ADD,
0x85 => CpuOpcode::ADD,
0x86 => CpuOpcode::ADD,
0xC6 => CpuOpcode::ADD,
0x8F => CpuOpcode::ADC,
0x88 => CpuOpcode::ADC,
0x89 => CpuOpcode::ADC,
0x8A => CpuOpcode::ADC,
0x8B => CpuOpcode::ADC,
0x8C => CpuOpcode::ADC,
0x8D => CpuOpcode::ADC,
0x8E => CpuOpcode::ADC,
0xCE => CpuOpcode::ADC,
0x97 => CpuOpcode::SUB,
0x90 => CpuOpcode::SUB,
0x91 => CpuOpcode::SUB,
0x92 => CpuOpcode::SUB,
0x93 => CpuOpcode::SUB,
0x94 => CpuOpcode::SUB,
0x95 => CpuOpcode::SUB,
0x96 => CpuOpcode::SUB,
0xD6 => CpuOpcode::SUB,
0x9F => CpuOpcode::SBC,
0x98 => CpuOpcode::SBC,
0x99 => CpuOpcode::SBC,
0x9A => CpuOpcode::SBC,
0x9B => CpuOpcode::SBC,
0x9C => CpuOpcode::SBC,
0x9D => CpuOpcode::SBC,
0x9E => CpuOpcode::SBC,
0xA7 => CpuOpcode::AND,
0xA0 => CpuOpcode::AND,
0xA1 => CpuOpcode::AND,
0xA2 => CpuOpcode::AND,
0xA3 => CpuOpcode::AND,
0xA4 => CpuOpcode::AND,
0xA5 => CpuOpcode::AND,
0xA6 => CpuOpcode::AND,
0xE6 => CpuOpcode::AND,
0xB7 => CpuOpcode::OR,
0xB0 => CpuOpcode::OR,
0xB1 => CpuOpcode::OR,
0xB2 => CpuOpcode::OR,
0xB3 => CpuOpcode::OR,
0xB4 => CpuOpcode::OR,
0xB5 => CpuOpcode::OR,
0xB6 => CpuOpcode::OR,
0xF6 => CpuOpcode::OR,
0xAF => CpuOpcode::XOR,
0xA8 => CpuOpcode::XOR,
0xA9 => CpuOpcode::XOR,
0xAA => CpuOpcode::XOR,
0xAB => CpuOpcode::XOR,
0xAC => CpuOpcode::XOR,
0xAD => CpuOpcode::XOR,
0xAE => CpuOpcode::XOR,
0xEE => CpuOpcode::XOR,
0xBF => CpuOpcode::CP,
0xB8 => CpuOpcode::CP,
0xB9 => CpuOpcode::CP,
0xBA => CpuOpcode::CP,
0xBB => CpuOpcode::CP,
0xBC => CpuOpcode::CP,
0xBD => CpuOpcode::CP,
0xBE => CpuOpcode::CP,
0xFE => CpuOpcode::CP,
0x3C => CpuOpcode::INC,
0x04 => CpuOpcode::INC,
0x0C => CpuOpcode::INC,
0x14 => CpuOpcode::INC,
0x1C => CpuOpcode::INC,
0x24 => CpuOpcode::INC,
0x2C => CpuOpcode::INC,
0x34 => CpuOpcode::INC,
0x3D => CpuOpcode::DEC,
0x05 => CpuOpcode::DEC,
0x0D => CpuOpcode::DEC,
0x15 => CpuOpcode::DEC,
0x1D => CpuOpcode::DEC,
0x25 => CpuOpcode::DEC,
0x2D => CpuOpcode::DEC,
0x35 => CpuOpcode::DEC,
0x09 => CpuOpcode::ADD,
0x19 => CpuOpcode::ADD,
0x29 => CpuOpcode::ADD,
0x39 => CpuOpcode::ADD,
0xE8 => CpuOpcode::ADD,
0x03 => CpuOpcode::INC,
0x13 => CpuOpcode::INC,
0x23 => CpuOpcode::INC,
0x33 => CpuOpcode::INC,
0x0B => CpuOpcode::DEC,
0x1B => CpuOpcode::DEC,
0x2B => CpuOpcode::DEC,
0x3B => CpuOpcode::DEC,
0xCB => CpuOpcode::SWAP,
0x27 => CpuOpcode::DAA,
0x2F => CpuOpcode::CPL,
0x3F => CpuOpcode::CCF,
0x37 => CpuOpcode::SCF,
0x17 => CpuOpcode::RLA,
0x07 => CpuOpcode::RLCA,
0x0F => CpuOpcode::RRCA,
0x1F => CpuOpcode::RRA,
//0xCB => CpuOpcode::RLC,
//0xCB => CpuOpcode::RL,
//0xCB => CpuOpcode::RRC,
//0xCB => CpuOpcode::RR,
//0xCB => CpuOpcode::SLA,
//0xCB => CpuOpcode::SRA,
//0xCB => CpuOpcode::SRL,
//0xCB => CpuOpcode::BIT,
//0xCB => CpuOpcode::SET,
//0xCB => CpuOpcode::RES,
0xC3 => CpuOpcode::JP,
0xC2 => CpuOpcode::JP,
0xCA => CpuOpcode::JP,
0xD2 => CpuOpcode::JP,
0xDA => CpuOpcode::JP,
0xE9 => CpuOpcode::JP,
0x18 => CpuOpcode::JR,
0x20 => CpuOpcode::JR,
0x28 => CpuOpcode::JR,
0x30 => CpuOpcode::JR,
0x38 => CpuOpcode::JR,
0xCD => CpuOpcode::CALL,
0xC4 => CpuOpcode::CALL,
0xCC => CpuOpcode::CALL,
0xD4 => CpuOpcode::CALL,
0xDC => CpuOpcode::CALL,
0xC7 => CpuOpcode::RST,
0xCF => CpuOpcode::RST,
0xD7 => CpuOpcode::RST,
0xDF => CpuOpcode::RST,
0xE7 => CpuOpcode::RST,
0xEF => CpuOpcode::RST,
0xF7 => CpuOpcode::RST,
0xFF => CpuOpcode::RST,
0xC9 => CpuOpcode::RET,
0xC0 => CpuOpcode::RET,
0xC8 => CpuOpcode::RET,
0xD0 => CpuOpcode::RET,
0xD8 => CpuOpcode::RET,
0xD9 => CpuOpcode::RETI,
0xF3 => CpuOpcode::DI,
0xFB => CpuOpcode::EI,
0x76 => CpuOpcode::HALT,
0x10 => CpuOpcode::STOP,
0x00 => CpuOpcode::NOP,
_ => CpuOpcode::NOP,
}
}
}
#[cfg(test)]
mod tests {