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Refactor register bit length detection
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parent
dbe95bedf2
commit
c55256a5b7
38
src/cpu.rs
38
src/cpu.rs
@ -28,6 +28,21 @@ pub enum Register {
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PC, // Program counter
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PC, // Program counter
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}
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}
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type Rg = Register;
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impl Register {
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pub fn is_8bit(&self) -> bool {
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match self {
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Rg::A | Rg::F | Rg::B | Rg::C | Rg::D | Rg::E | Rg::H | Rg::L => true,
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Rg::AF | Rg::BC | Rg::DE | Rg::HL | Rg::SP | Rg::PC => false,
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}
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}
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pub fn is_16bit(&self) -> bool {
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!self.is_8bit()
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}
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}
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#[derive(Debug, Copy, Clone)]
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#[derive(Debug, Copy, Clone)]
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pub enum FlagRegister {
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pub enum FlagRegister {
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Zero, // Set when the result of a math operation is zero or if two values matches using the CP instruction
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Zero, // Set when the result of a math operation is zero or if two values matches using the CP instruction
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@ -275,14 +290,11 @@ impl CPU {
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self.registers.increment(Register::PC, 3);
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self.registers.increment(Register::PC, 3);
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},
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},
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OpcodeParameter::U16_Register(address, register) => {
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OpcodeParameter::U16_Register(address, register) => {
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type Rg = Register;
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let value = self.registers.get(register);
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let value = self.registers.get(register);
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let bytes = value.to_be_bytes();
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let bytes = value.to_be_bytes();
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match register {
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match register.is_8bit() {
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Rg::A | Rg::F | Rg::B | Rg::C | Rg::D | Rg::E | Rg::H | Rg::L => {
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true => bus.write(address, bytes[1]),
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bus.write(address, bytes[1]);
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false => {
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},
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Rg::AF | Rg::BC | Rg::DE | Rg::HL | Rg::SP | Rg::PC => {
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bus.write(address, bytes[1]);
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bus.write(address, bytes[1]);
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bus.write(address + 1, bytes[0]);
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bus.write(address + 1, bytes[0]);
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}
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}
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@ -297,7 +309,12 @@ impl CPU {
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self.registers.increment(register, 1);
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self.registers.increment(register, 1);
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if affect_flags {
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if affect_flags {
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self.registers.set_flag(FlagRegister::Substract, false);
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self.registers.set_flag(FlagRegister::Substract, false);
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if add_half_carry(prev_value.to_be_bytes()[1], 1) {
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let mut byte_compare = 0;
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match register.is_8bit() {
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true => byte_compare = prev_value.to_be_bytes()[1],
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false => byte_compare = prev_value.to_be_bytes()[0],
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}
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if add_half_carry(byte_compare, 1) {
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self.registers.set_flag(FlagRegister::HalfCarry, true);
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self.registers.set_flag(FlagRegister::HalfCarry, true);
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}
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}
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let result = self.registers.get(register);
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let result = self.registers.get(register);
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@ -313,7 +330,12 @@ impl CPU {
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self.registers.decrement(register, 1);
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self.registers.decrement(register, 1);
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if affect_flags {
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if affect_flags {
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self.registers.set_flag(FlagRegister::Substract, true);
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self.registers.set_flag(FlagRegister::Substract, true);
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if sub_half_carry(prev_value.to_be_bytes()[1], 1) {
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let mut byte_compare = 0;
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match register.is_8bit() {
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true => byte_compare = prev_value.to_be_bytes()[1],
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false => byte_compare = prev_value.to_be_bytes()[0],
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}
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if sub_half_carry(byte_compare, 1) {
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self.registers.set_flag(FlagRegister::HalfCarry, true);
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self.registers.set_flag(FlagRegister::HalfCarry, true);
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}
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}
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let result = self.registers.get(register);
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let result = self.registers.get(register);
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