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One more test with bus

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This commit is contained in:
Franco Colmenarez 2021-10-18 10:33:59 -05:00
parent aad827f05f
commit d093aa483d
1 changed files with 44 additions and 4 deletions
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48
src/cpu.rs
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@ -744,22 +744,36 @@ impl CPU {
self.registers.set_flag(FlagRegister::Carry, get_bit(result, BitIndex::I0));
},
Opcode::RL(register) => {
let val = self.registers.get_8bit(register);
let mut val = 0;
match register.is_8bit() {
true => val = self.registers.get_8bit(register),
false => val = bus.read(self.registers.get(register)),
};
let old_carry = self.registers.get_flag(FlagRegister::Carry);
let new_carry = get_bit(val, BitIndex::I1);
let val = val >> 2 | ((old_carry as u8) << 6) | (val << 7);
self.registers.set(register, val as u16);
match register.is_8bit() {
true => self.registers.set(register, val as u16),
false => bus.write(self.registers.get(register), val),
};
self.registers.set_flag(FlagRegister::Carry, new_carry);
self.registers.set_flag(FlagRegister::Zero, val == 0);
self.registers.set_flag(FlagRegister::Substract, false);
self.registers.set_flag(FlagRegister::HalfCarry, false);
},
Opcode::RR(register) => {
let val = self.registers.get_8bit(register);
let mut val = 0;
match register.is_8bit() {
true => val = self.registers.get_8bit(register),
false => val = bus.read(self.registers.get(register)),
};
let old_carry = self.registers.get_flag(FlagRegister::Carry);
let new_carry = get_bit(val, BitIndex::I6);
let val = val << 2 | ((old_carry as u8) << 1) | (val >> 7);
self.registers.set(register, val as u16);
match register.is_8bit() {
true => self.registers.set(register, val as u16),
false => bus.write(self.registers.get(register), val),
};
self.registers.set_flag(FlagRegister::Carry, new_carry);
self.registers.set_flag(FlagRegister::Zero, val == 0);
self.registers.set_flag(FlagRegister::Substract, false);
@ -2312,6 +2326,19 @@ mod tests {
assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
assert_eq!(cpu.registers.get(Register::A), 0b00000000);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
let mut cpu = CPU::new();
let addr = 0xC000;
bus.write(addr, 0b00000010);
cpu.registers.set(Register::HL, addr);
cpu.registers.set_flag(FlagRegister::Carry, false);
cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RL(Register::HL))), &mut bus);
assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
assert_eq!(bus.read(addr), 0b00000000);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
}
#[test]
@ -2349,6 +2376,19 @@ mod tests {
assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
assert_eq!(cpu.registers.get(Register::A), 0b00000000);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
let mut cpu = CPU::new();
let addr = 0xC000;
bus.write(addr, 0b01000000);
cpu.registers.set(Register::HL, addr);
cpu.registers.set_flag(FlagRegister::Carry, false);
cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RR(Register::HL))), &mut bus);
assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
assert_eq!(bus.read(addr), 0b00000000);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
}
#[test]