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Another LD instruction

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This commit is contained in:
Franco Colmenarez 2021-10-16 14:50:01 -05:00
parent f94314ad01
commit d24f048c86
1 changed files with 28 additions and 0 deletions
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28
src/cpu.rs
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@ -344,6 +344,17 @@ impl CPU {
} }
self.registers.increment(Register::PC, 3); self.registers.increment(Register::PC, 3);
}, },
OpcodeParameter::Register_FF00plusU8(register, val) => {
self.registers.set(register, bus.read(0xFF00 + (val as u16)) as u16);
self.registers.increment(Register::PC, 2);
},
OpcodeParameter::FF00plusU8_Register(val, register) => {
match register.is_8bit() {
true => bus.write(0xFF00 + (val as u16), self.registers.get(register).to_be_bytes()[1]),
false => bus.write_16bit(0xFF00 + (val as u16), self.registers.get(register)),
}
self.registers.increment(Register::PC, 2);
},
_ => {}, _ => {},
}, },
// Increment or decrement program counter by signed N // Increment or decrement program counter by signed N
@ -856,6 +867,23 @@ mod tests {
assert_eq!(cpu.registers.get(Register::A), 0xFF); assert_eq!(cpu.registers.get(Register::A), 0xFF);
assert_eq!(cpu.registers.get(Register::PC), 0x101); assert_eq!(cpu.registers.get(Register::PC), 0x101);
let mut cpu = CPU::new();
let mut bus = Bus::new();
let addr = 0xFF00;
cpu.registers.set(Register::A, 0xF1);
cpu.exec(Opcode::LD(OpcodeParameter::FF00plusU8_Register(4, Register::A)), &mut bus);
assert_eq!(bus.read(addr + 4), 0xF1);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
let mut cpu = CPU::new();
let mut bus = Bus::new();
let addr = 0xFF00;
cpu.registers.set(Register::A, 0x00);
bus.write(addr + 4, 0xF1);
cpu.exec(Opcode::LD(OpcodeParameter::Register_FF00plusU8(Register::A, 4)), &mut bus);
assert_eq!(cpu.registers.get(Register::A), 0xF1);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
// LDI // LDI
let mut bus = Bus::new(); let mut bus = Bus::new();
let mut cpu = CPU::new(); let mut cpu = CPU::new();