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Emulate Echo RAM
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23
src/bus.rs
23
src/bus.rs
@ -57,7 +57,12 @@ impl Bus {
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match MemoryMap::get_map(address) {
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match MemoryMap::get_map(address) {
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MemoryMap::BankZero => self.game_rom.read(address),
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MemoryMap::BankZero => self.game_rom.read(address),
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MemoryMap::BankSwitchable => self.game_rom.read(address),
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MemoryMap::BankSwitchable => self.game_rom.read(address),
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// MemoryMap::InterruptEnableRegister => self.data[address as usize],
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MemoryMap::WorkRAM1 | MemoryMap::WorkRAM2 | MemoryMap::InterruptEnableRegister => self.data[address as usize],
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MemoryMap::IORegisters => match address {
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0xFF44 => 0x90,
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0xFF4D => 0xFF,
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_ => self.data[address as usize],
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}
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_ => self.data[address as usize],
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_ => self.data[address as usize],
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}
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}
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}
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}
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@ -67,7 +72,21 @@ impl Bus {
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}
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}
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pub fn write(&mut self, address: u16, data: u8) {
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pub fn write(&mut self, address: u16, data: u8) {
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self.data[address as usize] = data;
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match MemoryMap::get_map(address) {
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MemoryMap::WorkRAM1 | MemoryMap::WorkRAM2 => {
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self.data[address as usize] = data;
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// Copy to the ECHO RAM
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if address <= 0xDDFF {
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self.data[(0xE000 + (address - 0xC000)) as usize] = data;
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}
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},
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MemoryMap::EchoRAM => {
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self.data[address as usize] = data;
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// Copy to the working RAM
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self.data[(0xC000 + (address - 0xE000)) as usize] = data;
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},
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_ => self.data[address as usize] = data,
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};
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}
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}
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pub fn write_16bit(&mut self, address: u16, data: u16) {
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pub fn write_16bit(&mut self, address: u16, data: u16) {
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