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RES instruction
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parent
edc8429aa2
commit
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32
src/cpu.rs
32
src/cpu.rs
@ -998,6 +998,18 @@ impl CPU {
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self.registers.set_flag(FlagRegister::Substract, false);
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self.registers.set_flag(FlagRegister::HalfCarry, true);
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},
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Opcode::RES(index, register) => {
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let mut val = 0;
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match register.is_8bit() {
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true => val = self.registers.get_8bit(register),
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false => val = bus.read(self.registers.get(register)),
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};
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let val = set_bit(val, false, index);
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match register.is_8bit() {
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true => self.registers.set(register, val as u16),
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false => bus.write(self.registers.get(register), val),
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};
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},
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_ => {},
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};
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},
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@ -2890,7 +2902,6 @@ mod tests {
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut bus = Bus::new();
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0b11110101);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::A))), &mut bus);
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@ -2899,7 +2910,6 @@ mod tests {
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut bus = Bus::new();
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let mut cpu = CPU::new();
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let addr = 0xC000;
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cpu.registers.set(Register::HL, addr);
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@ -2911,6 +2921,24 @@ mod tests {
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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}
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#[test]
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fn test_prefix_cb_res_instruction() {
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let mut bus = Bus::new();
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0b11110101);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::A))), &mut bus);
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assert_eq!(cpu.registers.get_8bit(Register::A), 0b11110001);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut cpu = CPU::new();
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let addr = 0xC000;
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cpu.registers.set(Register::HL, addr);
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bus.write(addr, 0b11110101);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0 ,Register::HL))), &mut bus);
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assert_eq!(bus.read(addr), 0b11110100);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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}
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#[test]
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fn test_daa_instruction() {
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let mut bus = Bus::new();
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