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RES instruction

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This commit is contained in:
Franco Colmenarez 2021-10-19 10:02:43 -05:00
parent edc8429aa2
commit e4586db39a
1 changed files with 30 additions and 2 deletions
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32
src/cpu.rs
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@ -998,6 +998,18 @@ impl CPU {
self.registers.set_flag(FlagRegister::Substract, false); self.registers.set_flag(FlagRegister::Substract, false);
self.registers.set_flag(FlagRegister::HalfCarry, true); self.registers.set_flag(FlagRegister::HalfCarry, true);
}, },
Opcode::RES(index, register) => {
let mut val = 0;
match register.is_8bit() {
true => val = self.registers.get_8bit(register),
false => val = bus.read(self.registers.get(register)),
};
let val = set_bit(val, false, index);
match register.is_8bit() {
true => self.registers.set(register, val as u16),
false => bus.write(self.registers.get(register), val),
};
},
_ => {}, _ => {},
}; };
}, },
@ -2890,7 +2902,6 @@ mod tests {
assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true); assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
assert_eq!(cpu.registers.get(Register::PC), 0x102); assert_eq!(cpu.registers.get(Register::PC), 0x102);
let mut bus = Bus::new();
let mut cpu = CPU::new(); let mut cpu = CPU::new();
cpu.registers.set(Register::A, 0b11110101); cpu.registers.set(Register::A, 0b11110101);
cpu.exec(Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::A))), &mut bus); cpu.exec(Opcode::PrefixCB(Box::new(Opcode::BIT(BitIndex::I4, Register::A))), &mut bus);
@ -2899,7 +2910,6 @@ mod tests {
assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true); assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
assert_eq!(cpu.registers.get(Register::PC), 0x102); assert_eq!(cpu.registers.get(Register::PC), 0x102);
let mut bus = Bus::new();
let mut cpu = CPU::new(); let mut cpu = CPU::new();
let addr = 0xC000; let addr = 0xC000;
cpu.registers.set(Register::HL, addr); cpu.registers.set(Register::HL, addr);
@ -2911,6 +2921,24 @@ mod tests {
assert_eq!(cpu.registers.get(Register::PC), 0x102); assert_eq!(cpu.registers.get(Register::PC), 0x102);
} }
#[test]
fn test_prefix_cb_res_instruction() {
let mut bus = Bus::new();
let mut cpu = CPU::new();
cpu.registers.set(Register::A, 0b11110101);
cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I2, Register::A))), &mut bus);
assert_eq!(cpu.registers.get_8bit(Register::A), 0b11110001);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
let mut cpu = CPU::new();
let addr = 0xC000;
cpu.registers.set(Register::HL, addr);
bus.write(addr, 0b11110101);
cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RES(BitIndex::I0 ,Register::HL))), &mut bus);
assert_eq!(bus.read(addr), 0b11110100);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
}
#[test] #[test]
fn test_daa_instruction() { fn test_daa_instruction() {
let mut bus = Bus::new(); let mut bus = Bus::new();