diff --git a/src/bus.rs b/src/bus.rs
index 3150c41..b20b216 100644
--- a/src/bus.rs
+++ b/src/bus.rs
@@ -48,7 +48,7 @@ impl Bus {
             _ => ROM::from_bytes(&[0; 0xFFFF])
         };
         Self {
-            data: [0; 0x10000],
+            data: [0xFF; 0x10000],
             game_rom,
         }
     }
@@ -73,6 +73,9 @@ impl Bus {
 
     pub fn write(&mut self, address: u16, data: u8) {
         match MemoryMap::get_map(address) {
+            MemoryMap::BankZero | MemoryMap::BankSwitchable => {
+                // println!("WRITING TO ROM");
+            },
             MemoryMap::WorkRAM1 | MemoryMap::WorkRAM2 => {
                 self.data[address as usize] = data;
                 // Copy to the ECHO RAM
@@ -82,8 +85,7 @@ impl Bus {
             },
             MemoryMap::EchoRAM => {
                 self.data[address as usize] = data;
-                // Copy to the working RAM
-                self.data[(0xC000 + (address - 0xE000)) as usize] = data;
+                self.data[(0xC000 + (address - 0xE000)) as usize] = data; // Copy to the working RAM
             },
             _ => self.data[address as usize] = data,
         };
diff --git a/src/cpu.rs b/src/cpu.rs
index 5b2a8c3..84409a4 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -328,7 +328,10 @@ impl CPU {
                     self.registers.increment(Register::PC, 1);
                 },
                 OpcodeParameter::Register_U16(register, val) => {
-                    self.registers.set(register, val);
+                    match register.is_8bit() {
+                        true => self.registers.set(register, bus.read(val) as u16),
+                        false => self.registers.set(register, val),
+                    };
                     self.registers.increment(Register::PC, 3);
                 },
                 OpcodeParameter::Register_U8(register, val) => {
@@ -942,6 +945,14 @@ mod tests {
         assert_eq!(cpu.registers.get(Register::SP), 0xF1F1);
         assert_eq!(cpu.registers.get(Register::PC), 0x103);
 
+        let mut cpu = CPU::new();
+        let mut bus = Bus::new();
+        let addr = 0xC000;
+        bus.write(addr, 0xF1);
+        cpu.exec(Opcode::LD(OpcodeParameter::Register_U16(Register::A, addr)), &mut bus);
+        assert_eq!(cpu.registers.get(Register::A), 0xF1);
+        assert_eq!(cpu.registers.get(Register::PC), 0x103);
+
         let mut cpu = CPU::new();
         let mut bus = Bus::new();
         cpu.exec(Opcode::LD(OpcodeParameter::Register_U8(Register::B, 0xF1)), &mut bus);