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ADD instruction bug
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parent
ac91f8f50d
commit
eeeba76ebd
142
src/cpu.rs
142
src/cpu.rs
@ -233,8 +233,8 @@ pub enum Opcode {
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OR(OpcodeParameter),
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XOR(OpcodeParameter),
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CP(OpcodeParameter),
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INC(bool, Register),
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DEC(bool, Register),
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INC(bool, bool, Register),
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DEC(bool, bool, Register),
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DAA,
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CPL,
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CCF,
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@ -528,6 +528,7 @@ impl CPU {
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if reg1.is_8bit() && reg2.is_8bit() {
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self.registers.set_flag(FlagRegister::HalfCarry, add_half_carry(self.registers.get_8bit(reg1), self.registers.get_8bit(reg2)));
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self.registers.set(reg1, self.registers.get(reg1) + self.registers.get(reg2));
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self.registers.set_flag(FlagRegister::Zero, self.registers.get(reg1) == 0);
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} else if reg1.is_16bit() && reg2.is_16bit() {
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self.registers.set_flag(FlagRegister::HalfCarry, add_half_carry_16bit(self.registers.get(reg1), self.registers.get(reg2)));
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self.registers.set(reg1, self.registers.get(reg1) + self.registers.get(reg2));
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@ -536,8 +537,8 @@ impl CPU {
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let val2 = bus.read(self.registers.get(reg2)) as u16;
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self.registers.set(reg1, val1 + val2);
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self.registers.set_flag(FlagRegister::HalfCarry, add_half_carry(val1.to_be_bytes()[1], val2.to_be_bytes()[1]));
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}
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self.registers.set_flag(FlagRegister::Zero, self.registers.get(reg1) == 0);
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}
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self.registers.set_flag(FlagRegister::Carry, self.registers.get(reg1) == 0);
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},
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OpcodeParameter::Register_U8(reg1, val) => {
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@ -638,46 +639,60 @@ impl CPU {
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_ => {},
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},
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// Increment by 1
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Opcode::INC(affect_flags, register) => {
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Opcode::INC(affect_flags, on_address, register) => {
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self.registers.increment(Register::PC, 1);
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let mut prev_value = 0;
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let mut result = 0;
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if register.is_8bit() {
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prev_value = self.registers.get_8bit(register);
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self.registers.increment(register, 1);
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result = self.registers.get_8bit(register);
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} else {
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if on_address {
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let addr = self.registers.get(register);
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prev_value = bus.read(addr);
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let prev_value = bus.read(addr);
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bus.write(addr, prev_value + 1);
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result = bus.read(addr);
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}
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if affect_flags {
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self.registers.set_flag(FlagRegister::Substract, false);
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self.registers.set_flag(FlagRegister::HalfCarry, add_half_carry(prev_value, 1));
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self.registers.set_flag(FlagRegister::Zero, bus.read(addr) == 0);
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}
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} else {
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let prev_value = self.registers.get(register);
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self.registers.increment(register, 1);
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if affect_flags {
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let mut byte_compare = 0;
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match register.is_8bit() {
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true => byte_compare = prev_value.to_be_bytes()[1],
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false => byte_compare = prev_value.to_be_bytes()[0],
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}
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let result = self.registers.get(register);
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self.registers.set_flag(FlagRegister::Substract, false);
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self.registers.set_flag(FlagRegister::HalfCarry, add_half_carry(byte_compare, 1));
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self.registers.set_flag(FlagRegister::Zero, result == 0);
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}
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}
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},
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// Decrement by 1
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Opcode::DEC(affect_flags, register) => {
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Opcode::DEC(affect_flags, on_address, register) => {
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self.registers.increment(Register::PC, 1);
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let mut prev_value = 0;
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let mut result = 0;
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if register.is_8bit() {
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prev_value = self.registers.get_8bit(register);
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self.registers.decrement(register, 1);
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result = self.registers.get_8bit(register);
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} else {
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if on_address {
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let addr = self.registers.get(register);
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prev_value = bus.read(addr);
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let prev_value = bus.read(addr);
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bus.write(addr, prev_value - 1);
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result = bus.read(addr);
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}
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if affect_flags {
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self.registers.set_flag(FlagRegister::Substract, true);
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self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(prev_value, 1));
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self.registers.set_flag(FlagRegister::Zero, bus.read(addr) == 0);
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}
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} else {
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let prev_value = self.registers.get(register);
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self.registers.decrement(register, 1);
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if affect_flags {
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let mut byte_compare = 0;
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match register.is_8bit() {
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true => byte_compare = prev_value.to_be_bytes()[1],
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false => byte_compare = prev_value.to_be_bytes()[0],
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}
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let result = self.registers.get(register);
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self.registers.set_flag(FlagRegister::Substract, true);
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self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(byte_compare, 1));
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self.registers.set_flag(FlagRegister::Zero, result == 0);
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}
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}
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},
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// Jump to address
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Opcode::JP(params) => match params {
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@ -1119,30 +1134,30 @@ impl CPU {
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0xBD => Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::L)),
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0xBE => Opcode::CP(OpcodeParameter::Register_Register(Register::A, Register::HL)),
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0xFE => Opcode::CP(OpcodeParameter::Register_U8(Register::A, params.1)),
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0x3C => Opcode::INC(true, Register::A),
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0x04 => Opcode::INC(true, Register::B),
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0x0C => Opcode::INC(true, Register::C),
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0x14 => Opcode::INC(true, Register::D),
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0x1C => Opcode::INC(true, Register::E),
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0x24 => Opcode::INC(true, Register::H),
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0x2C => Opcode::INC(true, Register::L),
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0x34 => Opcode::INC(true, Register::HL),
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0x03 => Opcode::INC(false, Register::BC),
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0x13 => Opcode::INC(false, Register::DE),
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0x23 => Opcode::INC(false, Register::HL),
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0x33 => Opcode::INC(false, Register::SP),
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0x3D => Opcode::DEC(true, Register::A),
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0x05 => Opcode::DEC(true, Register::B),
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0x0D => Opcode::DEC(true, Register::C),
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0x15 => Opcode::DEC(true, Register::D),
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0x1D => Opcode::DEC(true, Register::E),
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0x25 => Opcode::DEC(true, Register::H),
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0x2D => Opcode::DEC(true, Register::L),
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0x35 => Opcode::DEC(true, Register::HL),
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0x0B => Opcode::DEC(false, Register::BC),
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0x1B => Opcode::DEC(false, Register::DE),
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0x2B => Opcode::DEC(false, Register::HL),
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0x3B => Opcode::DEC(false, Register::SP),
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0x3C => Opcode::INC(true, false, Register::A),
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0x04 => Opcode::INC(true, false, Register::B),
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0x0C => Opcode::INC(true, false, Register::C),
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0x14 => Opcode::INC(true, false, Register::D),
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0x1C => Opcode::INC(true, false, Register::E),
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0x24 => Opcode::INC(true, false, Register::H),
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0x2C => Opcode::INC(true, false, Register::L),
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0x34 => Opcode::INC(true, true, Register::HL),
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0x03 => Opcode::INC(false, false, Register::BC),
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0x13 => Opcode::INC(false, false, Register::DE),
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0x23 => Opcode::INC(false, false, Register::HL),
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0x33 => Opcode::INC(false, false, Register::SP),
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0x3D => Opcode::DEC(true, false, Register::A),
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0x05 => Opcode::DEC(true, false, Register::B),
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0x0D => Opcode::DEC(true, false, Register::C),
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0x15 => Opcode::DEC(true, false, Register::D),
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0x1D => Opcode::DEC(true, false, Register::E),
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0x25 => Opcode::DEC(true, false, Register::H),
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0x2D => Opcode::DEC(true, false, Register::L),
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0x35 => Opcode::DEC(true, true, Register::HL),
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0x0B => Opcode::DEC(false, false, Register::BC),
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0x1B => Opcode::DEC(false, false, Register::DE),
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0x2B => Opcode::DEC(false, false, Register::HL),
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0x3B => Opcode::DEC(false, false, Register::SP),
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0x27 => Opcode::DAA,
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0x2F => Opcode::CPL,
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0x3F => Opcode::CCF,
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@ -2273,7 +2288,6 @@ mod tests {
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cpu.registers.set(Register::BC, 0b0000100000000000);
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cpu.registers.set(Register::HL, 0b0000100000000000);
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cpu.exec(Opcode::ADD(OpcodeParameter::Register_Register(Register::BC, Register::HL)), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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assert_eq!(cpu.registers.get(Register::BC), 0b0001000000000000);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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@ -2330,14 +2344,14 @@ mod tests {
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let mut bus = Bus::new();
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0);
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cpu.exec(Opcode::INC(true, Register::A), &mut bus);
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cpu.exec(Opcode::INC(true, false, Register::A), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0b00001111);
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cpu.exec(Opcode::INC(true, Register::A), &mut bus);
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cpu.exec(Opcode::INC(true, false, Register::A), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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@ -2346,12 +2360,20 @@ mod tests {
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let addr = 0xC000;
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cpu.registers.set(Register::HL, addr);
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bus.write(addr, 0b00001111);
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cpu.exec(Opcode::INC(true, Register::HL), &mut bus);
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cpu.exec(Opcode::INC(true, true, Register::HL), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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assert_eq!(bus.read(addr), 0b00010000);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::BC, 0b0000111111111111);
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cpu.exec(Opcode::INC(true, false, Register::BC), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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assert_eq!(cpu.registers.get(Register::BC), 0b0001000000000000);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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}
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#[test]
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@ -2359,7 +2381,7 @@ mod tests {
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let mut bus = Bus::new();
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 1);
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cpu.exec(Opcode::DEC(true, Register::A), &mut bus);
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cpu.exec(Opcode::DEC(true, false, Register::A), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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@ -2367,7 +2389,7 @@ mod tests {
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0b00010000);
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cpu.exec(Opcode::DEC(true, Register::A), &mut bus);
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cpu.exec(Opcode::DEC(true, false, Register::A), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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@ -2377,12 +2399,20 @@ mod tests {
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let addr = 0xC000;
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cpu.registers.set(Register::HL, addr);
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bus.write(addr, 0b00010000);
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cpu.exec(Opcode::DEC(true, Register::HL), &mut bus);
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cpu.exec(Opcode::DEC(true, true, Register::HL), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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assert_eq!(bus.read(addr), 0b00001111);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::BC, 0b0001000000000000);
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cpu.exec(Opcode::DEC(true, false, Register::BC), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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assert_eq!(cpu.registers.get(Register::BC), 0b0000111111111111);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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}
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#[test]
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