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https://github.com/FranLMSP/rmg-001.git
synced 2024-11-23 10:12:11 +00:00
Prefix CB RRC instruction
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ec34a71fcf
commit
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@ -2,7 +2,9 @@ use rust_boy::rom::ROM;
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use rust_boy::console::Console;
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fn main() -> std::io::Result<()> {
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let mut console = Console::new();
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console.cpu_run();
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/* let mut console = Console::new();
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console.cpu_run(); */
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let val: u8 = 0b00000001;
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println!("{:08b}", val.rotate_left(7));
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Ok(())
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}
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146
src/cpu.rs
146
src/cpu.rs
@ -713,21 +713,63 @@ impl CPU {
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}
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// Rotate A Left
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Opcode::RLCA => {
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self.registers.increment(Register::PC, 1);
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let val = self.registers.get(Register::A).to_be_bytes()[1];
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let result = val.rotate_left(7);
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if get_bit(result, BitIndex::I7) {
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self.registers.set_flag(FlagRegister::Carry, true);
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}
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self.registers.increment(Register::PC, 1);
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self.registers.set_flag(FlagRegister::Zero, false);
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self.registers.set_flag(FlagRegister::Substract, false);
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self.registers.set_flag(FlagRegister::HalfCarry, false);
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self.registers.set_flag(FlagRegister::Carry, get_bit(result, BitIndex::I7));
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},
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// Rotate A Right
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Opcode::RRCA => {
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let val = self.registers.get(Register::A).to_be_bytes()[1];
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let result = val.rotate_right(7);
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if get_bit(result, BitIndex::I0) {
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self.registers.set_flag(FlagRegister::Carry, true);
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}
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self.registers.increment(Register::PC, 1);
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let val = self.registers.get_8bit(Register::A);
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let result = val.rotate_right(7);
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self.registers.set_flag(FlagRegister::Zero, false);
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self.registers.set_flag(FlagRegister::Substract, false);
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self.registers.set_flag(FlagRegister::HalfCarry, false);
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self.registers.set_flag(FlagRegister::Carry, get_bit(result, BitIndex::I0));
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},
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Opcode::PrefixCB(opcode) => {
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self.registers.increment(Register::PC, 2);
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match *opcode {
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Opcode::RLC(register) => {
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let mut result = 0;
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if register.is_8bit() {
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let val = self.registers.get_8bit(register);
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result = val.rotate_left(7);
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self.registers.set(register, result as u16);
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} else {
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let addr = self.registers.get(register);
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let val = bus.read(addr);
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result = val.rotate_left(7);
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bus.write(addr, result);
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}
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self.registers.set_flag(FlagRegister::Zero, result == 0);
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self.registers.set_flag(FlagRegister::Substract, false);
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self.registers.set_flag(FlagRegister::HalfCarry, false);
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self.registers.set_flag(FlagRegister::Carry, get_bit(result, BitIndex::I7));
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},
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Opcode::RRC(register) => {
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let mut result = 0;
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if register.is_8bit() {
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let val = self.registers.get_8bit(register);
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result = val.rotate_right(7);
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self.registers.set(register, result as u16);
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} else {
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let addr = self.registers.get(register);
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let val = bus.read(addr);
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result = val.rotate_right(7);
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bus.write(addr, result);
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}
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self.registers.set_flag(FlagRegister::Zero, result == 0);
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self.registers.set_flag(FlagRegister::Substract, false);
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self.registers.set_flag(FlagRegister::HalfCarry, false);
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self.registers.set_flag(FlagRegister::Carry, get_bit(result, BitIndex::I0));
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},
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_ => {},
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};
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},
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// Disable interrupts
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Opcode::DI => {
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@ -2174,6 +2216,92 @@ mod tests {
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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}
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#[test]
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fn test_prefix_cb_rlc_instruction() {
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let mut bus = Bus::new();
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0b00000001);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RLC(Register::A))), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
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assert_eq!(cpu.registers.get(Register::A), 0b10000000);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0b01000000);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RLC(Register::A))), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
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assert_eq!(cpu.registers.get(Register::A), 0b00100000);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RLC(Register::A))), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
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assert_eq!(cpu.registers.get(Register::A), 0);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut cpu = CPU::new();
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let addr = 0xC000;
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cpu.registers.set(Register::HL, addr);
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bus.write(addr, 0b00000001);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RLC(Register::HL))), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
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assert_eq!(bus.read(addr), 0b10000000);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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}
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#[test]
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fn test_prefix_cb_rrc_instruction() {
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let mut bus = Bus::new();
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0b10000000);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RRC(Register::A))), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
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assert_eq!(cpu.registers.get(Register::A), 0b00000001);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0b00000010);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RRC(Register::A))), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
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assert_eq!(cpu.registers.get(Register::A), 0b00000100);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RRC(Register::A))), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
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assert_eq!(cpu.registers.get(Register::A), 0);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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let mut cpu = CPU::new();
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let addr = 0xC000;
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cpu.registers.set(Register::HL, addr);
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bus.write(addr, 0b10000000);
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cpu.exec(Opcode::PrefixCB(Box::new(Opcode::RRC(Register::HL))), &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
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assert_eq!(bus.read(addr), 0b00000001);
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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}
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#[test]
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fn test_nop_instructions() {
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let mut cpu = CPU::new();
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