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WIP DAA instruction
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commit
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71
src/cpu.rs
71
src/cpu.rs
@ -694,8 +694,33 @@ impl CPU {
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}
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}
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},
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// BCD correction
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Opcode::DAA => {
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self.registers.increment(Register::PC, 1);
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let mut val = self.registers.get_8bit(Register::A);
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// self.registers.set_flag(FlagRegister::Carry, false);
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self.registers.set_flag(FlagRegister::HalfCarry, false);
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if self.registers.get_flag(FlagRegister::Substract) {
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if self.registers.get_flag(FlagRegister::Carry) {
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val = val.wrapping_add(0x60);
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}
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if self.registers.get_flag(FlagRegister::HalfCarry) {
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val = val.wrapping_add(0x06);
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}
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} else {
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if self.registers.get_flag(FlagRegister::Carry) || val > 0x99 {
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val = val.wrapping_add(0x60);
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self.registers.set_flag(FlagRegister::Carry, true);
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}
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if self.registers.get_flag(FlagRegister::HalfCarry) || (val & 0x0F) > 0x09 {
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val = val.wrapping_add(0x06);
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}
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}
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// println!("{:02X} {:02X}", self.registers.get_8bit(Register::A), val);
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self.registers.set(Register::A, val as u16);
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self.registers.set_flag(FlagRegister::Zero, val == 0);
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},
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// Jump to address
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//
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Opcode::JP(params) => match params {
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OpcodeParameter::U16(address) => self.registers.set(Register::PC, address),
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OpcodeParameter::Register(register) => self.registers.set(Register::PC, self.registers.get(register)),
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@ -757,7 +782,10 @@ impl CPU {
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self.registers.increment(Register::PC, 1);
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let sp = self.registers.get(Register::SP);
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let val = bus.read_16bit(sp);
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self.registers.set(register, val);
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match register {
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Register::AF => self.registers.set(register, val & 0xFFF0),
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_ => self.registers.set(register, val),
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};
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self.registers.increment(Register::SP, 2);
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},
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// RET, same as POP PC when no parameter is specified
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@ -2787,6 +2815,45 @@ mod tests {
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assert_eq!(cpu.registers.get(Register::PC), 0x102);
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}
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#[test]
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fn test_daa_instruction() {
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let mut bus = Bus::new();
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0x0A);
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cpu.registers.set_flag(FlagRegister::Carry, false);
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cpu.exec(Opcode::DAA, &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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// assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
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assert_eq!(cpu.registers.get(Register::A), 0x10);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0x9A);
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cpu.exec(Opcode::DAA, &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
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assert_eq!(cpu.registers.get(Register::A), 0x00);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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let mut cpu = CPU::new();
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cpu.registers.set(Register::A, 0x00);
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cpu.registers.set_flag(FlagRegister::Zero, false);
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cpu.registers.set_flag(FlagRegister::Substract, false);
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cpu.registers.set_flag(FlagRegister::HalfCarry, true);
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cpu.registers.set_flag(FlagRegister::Carry, false);
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cpu.exec(Opcode::DAA, &mut bus);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
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assert_eq!(cpu.registers.get(Register::A), 0x06);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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}
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#[test]
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fn test_nop_instructions() {
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let mut cpu = CPU::new();
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