FranLMSP/rmg-001
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0xF8 instruction

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This commit is contained in:
Franco Colmenarez 2021-10-19 11:04:52 -05:00
parent 76684cd523
commit f928207a8d
3 changed files with 21 additions and 7 deletions
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6
src/bin/main.rs
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@ -2,9 +2,7 @@ use yargbe::rom::ROM;
use yargbe::console::Console; use yargbe::console::Console;
fn main() -> std::io::Result<()> { fn main() -> std::io::Result<()> {
/* let mut console = Console::new(); let mut console = Console::new();
console.cpu_run(); */ console.cpu_run();
let val: u8 = 0b11110000;
println!("{:08b}", !val);
Ok(()) Ok(())
} }

2
src/bus.rs
View File

@ -43,7 +43,7 @@ pub struct Bus {
impl Bus { impl Bus {
pub fn new() -> Self { pub fn new() -> Self {
let game_rom = match ROM::load_file("roms/cpu_instrs_individual/01-special.gb".to_string()) { let game_rom = match ROM::load_file("roms/cpu_instrs_individual/02-interrupts.gb".to_string()) {
Ok(rom) => rom, Ok(rom) => rom,
_ => ROM::from_bytes(&[0; 0xFFFF]) _ => ROM::from_bytes(&[0; 0xFFFF])
}; };

20
src/cpu.rs
View File

@ -197,7 +197,7 @@ pub enum OpcodeParameter {
Register_FF00plusU8(Register, u8), Register_FF00plusU8(Register, u8),
FF00plusU8_Register(u8, Register), FF00plusU8_Register(u8, Register),
Register_RegisterPlusI8(Register, Register, u8), Register_RegisterPlusI8(Register, Register, i8),
U8(u8), U8(u8),
I8(i8), I8(i8),
@ -364,6 +364,11 @@ impl CPU {
false => bus.write_16bit(0xFF00 + (val as u16), self.registers.get(register)), false => bus.write_16bit(0xFF00 + (val as u16), self.registers.get(register)),
} }
}, },
OpcodeParameter::Register_RegisterPlusI8(reg1, reg2, val) => {
self.registers.increment(Register::PC, 2);
let res = (self.registers.get(reg2) as i16) + (val as i16);
self.registers.set(reg1, res as u16);
},
_ => {}, _ => {},
}, },
// Increment or decrement program counter by signed N // Increment or decrement program counter by signed N
@ -1176,7 +1181,7 @@ impl CPU {
0x21 => Opcode::LD(OpcodeParameter::Register_U16(Register::HL, two_byte_param)), 0x21 => Opcode::LD(OpcodeParameter::Register_U16(Register::HL, two_byte_param)),
0x31 => Opcode::LD(OpcodeParameter::Register_U16(Register::SP, two_byte_param)), 0x31 => Opcode::LD(OpcodeParameter::Register_U16(Register::SP, two_byte_param)),
0xF9 => Opcode::LD(OpcodeParameter::Register_Register(Register::SP, Register::HL)), 0xF9 => Opcode::LD(OpcodeParameter::Register_Register(Register::SP, Register::HL)),
0xF8 => Opcode::LD(OpcodeParameter::Register_RegisterPlusI8(Register::HL, Register::SP, params.1)), 0xF8 => Opcode::LD(OpcodeParameter::Register_RegisterPlusI8(Register::HL, Register::SP, params.1 as i8)),
0x08 => Opcode::LD(OpcodeParameter::U16_Register(two_byte_param, Register::SP)), 0x08 => Opcode::LD(OpcodeParameter::U16_Register(two_byte_param, Register::SP)),
0xC5 => Opcode::PUSH(Register::BC), 0xC5 => Opcode::PUSH(Register::BC),
0xD5 => Opcode::PUSH(Register::DE), 0xD5 => Opcode::PUSH(Register::DE),
@ -1735,6 +1740,17 @@ mod tests {
cpu.exec(Opcode::LD(OpcodeParameter::Register_FF00plusU8(Register::A, 4)), &mut bus); cpu.exec(Opcode::LD(OpcodeParameter::Register_FF00plusU8(Register::A, 4)), &mut bus);
assert_eq!(cpu.registers.get(Register::A), 0xF1); assert_eq!(cpu.registers.get(Register::A), 0xF1);
assert_eq!(cpu.registers.get(Register::PC), 0x102); assert_eq!(cpu.registers.get(Register::PC), 0x102);
let mut cpu = CPU::new();
let mut bus = Bus::new();
cpu.registers.set(Register::PC, 100);
let mut cpu = CPU::new();
let val = 100;
cpu.registers.set(Register::SP, val);
cpu.exec(Opcode::LD(OpcodeParameter::Register_RegisterPlusI8(Register::HL, Register::SP, -5)), &mut bus);
assert_eq!(cpu.registers.get(Register::HL), val - 5);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
} }
#[test] #[test]