Commit Graph

33 Commits

Author SHA1 Message Date
292c7d1507 Basic joypad implementation 2021-10-31 21:02:09 -05:00
b5bb582c54 Tile fetch refactor and window pixel get 2021-10-31 17:03:59 -05:00
5723c3b3b6 Fix interrupts, implement halt mode and fix IME 2021-10-31 07:25:47 -05:00
61db367f31 Timer implement 2021-10-30 09:13:31 -05:00
abbd46ebed Refactor interrupt enum 2021-10-29 18:27:21 -05:00
66731e1c8e Refactor interrupt implementation 2021-10-29 17:03:02 -05:00
c77bc9db70 Experimental interrupts 2021-10-29 15:40:47 -05:00
f90900a4c1 Enabling lcd and vblank flag registers 2021-10-28 22:13:23 -05:00
7f9fdc9935 PPU timings 2021-10-28 19:38:30 -05:00
6ad3f9f29b Experimental background rendering with scrolling 2021-10-28 12:58:03 -05:00
ce4afa96bf Rendering tiles with a temporally algorithm 2021-10-28 10:30:48 -05:00
1444e8b63d Refactor address ranges 2021-10-22 15:32:12 -05:00
d655442b9a Prevent crashing on debug 2021-10-22 09:56:54 -05:00
d2bf668bdc Reducing some warnings 2021-10-20 18:24:13 -05:00
758772200f Some refactors on instructions 2021-10-20 18:16:45 -05:00
aa60d8586f Update project name again 2021-10-20 14:33:11 -05:00
bdd2b4659a Test rom 10 2021-10-20 13:47:59 -05:00
b154b4a5cb Fix some LD and rotate instructions 2021-10-20 13:39:39 -05:00
82fafad9cc Fix RST instruction 2021-10-20 12:29:55 -05:00
a4659dc147 Testing more roms 2021-10-19 22:36:10 -05:00
0a1f075734 Fix ADC and SBC instructions 2021-10-19 21:55:35 -05:00
8b287c17c7 Fix ADD carry 2021-10-19 13:59:53 -05:00
6b1d50ba76 Prevent panic on adding or sub with overflow on CPU 2021-10-19 13:17:14 -05:00
f928207a8d 0xF8 instruction 2021-10-19 11:04:52 -05:00
edc8429aa2 BIT instruction 2021-10-19 09:53:50 -05:00
ebadad803b Bug on LD instruction 2021-10-17 12:29:02 -05:00
e1d29d9530 Emulate Echo RAM 2021-10-17 12:02:33 -05:00
9d8d05c660 Including more test roms and initializing the registers 2021-10-15 19:49:36 -05:00
f9d5cfaa02 Refactor 16bit bus read write 2021-10-15 19:18:00 -05:00
253da76fd5 CALL u16 and RST instructions 2021-10-14 17:07:51 -05:00
a5fad87319 RLCA, LD and DI instructions 2021-10-14 13:25:20 -05:00
5d04b7c346 Modeling the Bus and writing first test for NOP instruction 2021-10-13 19:38:37 -05:00
2afa2a1ff8 Memory maps 2021-10-13 12:56:00 -05:00