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ce4afa96bf
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Rendering tiles with a temporally algorithm
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2021-10-28 10:30:48 -05:00 |
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1444e8b63d
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Refactor address ranges
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2021-10-22 15:32:12 -05:00 |
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d655442b9a
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Prevent crashing on debug
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2021-10-22 09:56:54 -05:00 |
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d2bf668bdc
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Reducing some warnings
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2021-10-20 18:24:13 -05:00 |
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758772200f
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Some refactors on instructions
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2021-10-20 18:16:45 -05:00 |
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aa60d8586f
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Update project name again
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2021-10-20 14:33:11 -05:00 |
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bdd2b4659a
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Test rom 10
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2021-10-20 13:47:59 -05:00 |
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b154b4a5cb
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Fix some LD and rotate instructions
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2021-10-20 13:39:39 -05:00 |
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82fafad9cc
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Fix RST instruction
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2021-10-20 12:29:55 -05:00 |
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a4659dc147
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Testing more roms
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2021-10-19 22:36:10 -05:00 |
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0a1f075734
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Fix ADC and SBC instructions
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2021-10-19 21:55:35 -05:00 |
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8b287c17c7
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Fix ADD carry
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2021-10-19 13:59:53 -05:00 |
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6b1d50ba76
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Prevent panic on adding or sub with overflow on CPU
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2021-10-19 13:17:14 -05:00 |
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f928207a8d
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0xF8 instruction
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2021-10-19 11:04:52 -05:00 |
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edc8429aa2
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BIT instruction
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2021-10-19 09:53:50 -05:00 |
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ebadad803b
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Bug on LD instruction
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2021-10-17 12:29:02 -05:00 |
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e1d29d9530
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Emulate Echo RAM
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2021-10-17 12:02:33 -05:00 |
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9d8d05c660
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Including more test roms and initializing the registers
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2021-10-15 19:49:36 -05:00 |
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f9d5cfaa02
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Refactor 16bit bus read write
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2021-10-15 19:18:00 -05:00 |
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253da76fd5
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CALL u16 and RST instructions
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2021-10-14 17:07:51 -05:00 |
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a5fad87319
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RLCA, LD and DI instructions
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2021-10-14 13:25:20 -05:00 |
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5d04b7c346
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Modeling the Bus and writing first test for NOP instruction
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2021-10-13 19:38:37 -05:00 |
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2afa2a1ff8
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Memory maps
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2021-10-13 12:56:00 -05:00 |
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