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No commits in common. "22c09895d787227e5d494372b7e0800dfead8d5c" and "569df9edd30ac6607cd782ae1685bab2d6637c01" have entirely different histories.

3 changed files with 38 additions and 159 deletions

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@ -16,12 +16,11 @@ Any help or suggestion is welcome!
- [x] NoMBC
- [x] MBC1
- [x] MBC2
- [ ] MBC3 (partially implemented)
- [X] MBC5
- [ ] MBC3
- [ ] MBC5
- [ ] MBC6
- [ ] MBC7
- [ ] HuC1
- [ ] Save files
- [ ] Web Assembly support (because this is a Rust project and it has to support Web Assembly)
- [ ] Gameboy boot ROM (Not important for now)
- [ ] Gameboy Color compatibility

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@ -306,7 +306,9 @@ impl PPU {
self.lcd_control = data;
// Check if LCD is being turned on or off
self.lcd_enable = get_bit(data, BitIndex::I7);
if !get_bit(data, BitIndex::I7) || (get_bit(data, BitIndex::I7) && !get_bit(self.lcd_control, BitIndex::I7)) {
if (get_bit(data, BitIndex::I7) && !get_bit(self.lcd_control, BitIndex::I7)) ||
!get_bit(data, BitIndex::I7)
{
self.io_registers[LCD_Y_ADDRESS as usize - 0xFF40] = 0x00;
// Set Hblank
let byte = self.io_registers[LCD_STATUS_ADDRESS as usize - 0xFF40];
@ -364,7 +366,6 @@ impl PPU {
}
} else if self.lcd_y >= 144 && !self.get_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::VBlank)) {
// Mode 1 Vertical blank
self.window_y_counter = 0;
self.set_lcd_status(LCDStatus::ModeFlag(LCDStatusModeFlag::VBlank), true);
self.set_interrupt(Interrupt::VBlank, true);
self.stat_interrupt();
@ -381,6 +382,7 @@ impl PPU {
// Frame completed
if self.lcd_y > 153 {
self.lcd_y = 0;
self.window_y_counter = 0;
}
self.force_set_register(LCD_Y_ADDRESS, self.lcd_y);
self.stat_interrupt();

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@ -65,7 +65,6 @@ pub fn load_rom(filename: &str) -> std::io::Result<Box<dyn ROM>> {
MBC::MBC1 => Box::new(MBC1::new(data, info)),
MBC::MBC2 => Box::new(MBC2::new(data, info)),
MBC::MBC3 => Box::new(MBC3::new(data, info)),
MBC::MBC5 => Box::new(MBC5::new(data, info)),
_ => unimplemented!(),
})
}
@ -92,7 +91,7 @@ enum Region {
NonJapanese,
}
#[derive(Debug, PartialEq)]
#[derive(Debug)]
enum BankingMode {
Simple,
Advanced,
@ -195,10 +194,6 @@ impl ROMInfo {
}
}
pub fn rom_size(&self) -> usize {
0x4000 * self.rom_banks as usize
}
pub fn ram_size(&self) -> usize {
0x2000 * self.ram_banks as usize
}
@ -245,7 +240,6 @@ pub struct MBC1 {
rom_bank: u16,
ram_bank: u8,
ram_enable: bool,
is_large_rom: bool,
banking_mode: BankingMode,
}
@ -256,8 +250,7 @@ impl MBC1 {
println!("Has RAM {}", info.has_ram);
println!("ROM banks {}", info.rom_banks);
println!("RAM banks {}", info.ram_banks);
let ram = vec![0; info.ram_size() as usize];
let is_large_rom = info.rom_size() >= 1048576;
let ram = Vec::with_capacity(info.ram_size() as usize);
Self {
data,
info,
@ -265,73 +258,31 @@ impl MBC1 {
rom_bank: 1,
ram_bank: 0,
ram_enable: false,
is_large_rom,
banking_mode: BankingMode::Simple,
}
}
fn switch_rom_bank(&mut self, bank: u8) {
self.rom_bank = bank as u16 & 0b11111;
if self.rom_bank == 0 {
self.rom_bank = 1;
}
fn switch_rom_bank(&mut self, bank: u16) {
self.rom_bank = bank;
if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
self.rom_bank = self.info.rom_banks.saturating_sub(1);
} else if self.rom_bank == 0 {
self.rom_bank = 1;
}
//println!("switched to ROM bank {}", self.rom_bank);
}
fn switch_ram_bank(&mut self, bank: u8) {
self.ram_bank = bank & 0b11;
// println!("switched to RAM bank {}", self.ram_bank);
}
fn get_bank_zero_address(&self, address: u16) -> usize {
if !self.is_large_rom {
return address as usize;
}
match self.banking_mode {
BankingMode::Simple => address as usize,
BankingMode::Advanced => {
((self.ram_bank as usize) << 5) * ((address & 0x3FFF) as usize)
},
}
}
fn get_bank_switchable_address(&self, address: u16) -> usize {
if self.is_large_rom {
let rom_bank = ((self.ram_bank as u16) << 5) | (self.rom_bank & 0b11111);
return ((rom_bank as usize) << 14) | (address & 0x3FFF) as usize;
}
return ((self.rom_bank as usize) << 14) | (address & 0x3FFF) as usize;
}
fn get_ram_address(&self, address: u16) -> usize {
let bank = match self.banking_mode {
BankingMode::Simple => 0,
BankingMode::Advanced => self.ram_bank,
};
((bank as usize) << 11) + ((address as usize) & 0x1FFF)
}
}
impl ROM for MBC1 {
fn read(&self, address: u16) -> u8 {
if BANK_ZERO.contains(&address) {
return match self.data.get(self.get_bank_zero_address(address)) {
Some(byte) => *byte,
None => 0xFF,
};
return self.data[address as usize];
} else if BANK_SWITCHABLE.contains(&address) {
return match self.data.get(self.get_bank_switchable_address(address)) {
Some(byte) => *byte,
None => 0xFF,
};
return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
} else if EXTERNAL_RAM.contains(&address) {
if !self.info.has_ram || !self.ram_enable {
if !self.info.has_ram {
return 0xFF;
}
return match self.ram.get(self.get_ram_address(address)) {
return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
Some(data) => *data,
None => 0xFF,
};
@ -350,22 +301,26 @@ impl ROM for MBC1 {
};
return;
} else if address >= 0x2000 && address <= 0x3FFF { // ROM bank number register
self.switch_rom_bank(data);
// println!("Switch bank to {:02X}", data);
self.switch_rom_bank(data as u16 & 0b00011111);
} else if address >= 0x4000 && address <= 0x5FFF { // ROM and RAM bank number register
self.switch_ram_bank(data);
// println!("RAM bank {:02X}", data);
self.ram_bank = data & 0b11;
} else if address >= 0x6000 && address <= 0x7FFF { // Banking mode select
self.banking_mode = match (data & 1) == 0 {
true => BankingMode::Simple,
false => BankingMode::Advanced,
self.banking_mode = match data & 1 {
0 => BankingMode::Simple,
1 => BankingMode::Advanced,
_ => unreachable!(),
}
} else if EXTERNAL_RAM.contains(&address) {
if !self.ram_enable || !self.info.has_ram {
return;
}
let address = self.get_ram_address(address);
let address = address as usize - EXTERNAL_RAM.min().unwrap() as usize + (EXTERNAL_RAM.min().unwrap() as usize * self.ram_bank as usize);
if let Some(elem) = self.ram.get_mut(address) {
*elem = data;
}
self.switch_rom_bank(self.rom_bank + (data as u16 >> 5));
}
}
}
@ -375,6 +330,7 @@ pub struct MBC2 {
info: ROMInfo,
ram: Vec<u8>,
rom_bank: u16,
ram_bank: u8,
ram_enable: bool,
}
@ -385,18 +341,19 @@ impl MBC2 {
println!("Has RAM {}", info.has_ram);
println!("ROM banks {}", info.rom_banks);
println!("RAM banks {}", info.ram_banks);
let ram = vec![0; 0x200];
let ram = Vec::with_capacity(info.ram_size() as usize);
Self {
data,
info,
ram,
rom_bank: 1,
ram_bank: 0,
ram_enable: false,
}
}
fn switch_rom_bank(&mut self, bank: u16) {
self.rom_bank = bank & 0b1111;
self.rom_bank = bank;
if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
self.rom_bank = self.info.rom_banks.saturating_sub(1);
} else if self.rom_bank == 0 {
@ -410,22 +367,23 @@ impl ROM for MBC2 {
if BANK_ZERO.contains(&address) {
return self.data[address as usize];
} else if BANK_SWITCHABLE.contains(&address) {
return self.data[((self.rom_bank as usize * 0x4000) + (address as usize % 0x4000)) as usize];
} else if address >= 0xA000 {
let address = (address as usize) & 0x1FF;
if !self.ram_enable {
return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
} else if address >= 0xA000 && address <= 0xA1FF {
if !self.info.has_ram || !self.ram_enable {
return 0xFF;
}
return match self.ram.get(address as usize) {
return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
Some(data) => *data,
None => 0xFF,
};
} else if address >= 0xA200 && address <= 0xBFFF {
return self.read(0xA000 + (address % 0x0200));
}
return 0xFF;
}
fn write(&mut self, address: u16, data: u8) {
if BANK_ZERO.contains(&address) {
if BANK_SWITCHABLE.contains(&address) {
if address.to_be_bytes()[0] & 1 == 0 {
match data {
0x0A => self.ram_enable = true,
@ -434,14 +392,6 @@ impl ROM for MBC2 {
} else {
self.switch_rom_bank(data as u16);
}
} else if address >= 0xA000 {
if !self.ram_enable {
return;
}
let address = address & 0x1FF;
if let Some(elem) = self.ram.get_mut(address as usize) {
*elem = data;
}
}
}
}
@ -462,7 +412,7 @@ impl MBC3 {
println!("Has RAM {}", info.has_ram);
println!("ROM banks {}", info.rom_banks);
println!("RAM banks {}", info.ram_banks);
let ram = vec![0; info.ram_size() as usize];
let ram = Vec::with_capacity(info.ram_size() as usize);
Self {
data,
info,
@ -521,75 +471,3 @@ impl ROM for MBC3 {
}
}
pub struct MBC5 {
data: Vec<u8>,
info: ROMInfo,
ram: Vec<u8>,
rom_bank: u16,
ram_bank: u8,
ram_enable: bool,
}
impl MBC5 {
fn new(data: Vec<u8>, info: ROMInfo) -> Self {
println!("MBC {:?}", info.mbc);
println!("Region {:?}", info.region);
println!("Has RAM {}", info.has_ram);
println!("ROM banks {}", info.rom_banks);
println!("RAM banks {}", info.ram_banks);
let ram = vec![0; info.ram_size() as usize];
Self {
data,
info,
ram,
rom_bank: 1,
ram_bank: 0,
ram_enable: false,
}
}
}
impl ROM for MBC5 {
fn read(&self, address: u16) -> u8 {
if BANK_ZERO.contains(&address) {
return self.data[address as usize];
} else if BANK_SWITCHABLE.contains(&address) {
return match self.data.get(((self.rom_bank as usize * 0x4000) + (address as usize % 0x4000)) as usize) {
Some(byte) => *byte,
None => 0xFF,
};
} else if EXTERNAL_RAM.contains(&address) {
if !self.info.has_ram || !self.ram_enable {
return 0xFF;
}
return match self.ram.get(((self.ram_bank as usize * 0x2000) + (address as usize % 0x2000)) as usize) {
Some(data) => *data,
None => 0xFF,
};
}
return 0xFF;
}
fn write(&mut self, address: u16, data: u8) {
if address <= 0x1FFF {
match data & 0b1111 {
0x0A => self.ram_enable = true,
_ => self.ram_enable = false,
};
} else if address >= 0x2000 && address <= 0x2FFF {
self.rom_bank = data as u16;
} else if address >= 0x3000 && address <= 0x3FFF {
self.rom_bank = ((data & 1) as u16) | (self.rom_bank & 0xF);
} else if address >= 0x4000 && address <= 0x5FFF {
self.ram_bank = data & 0b1111;
} else if EXTERNAL_RAM.contains(&address) {
if !self.ram_enable || !self.info.has_ram {
return;
}
if let Some(elem) = self.ram.get_mut(((self.ram_bank as usize * 0x2000) + (address as usize % 0x2000)) as usize) {
*elem = data;
}
}
}
}