FranLMSP/rmg-001
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base: FranLMSP:4caac23f66970ac83d198f83caf7626e699fe15a
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FranLMSP:main
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compare: FranLMSP:c009c65c45f13bfc598f92bcf5c01e62fc1b0834
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FranLMSP:main

No commits in common. "4caac23f66970ac83d198f83caf7626e699fe15a" and "c009c65c45f13bfc598f92bcf5c01e62fc1b0834" have entirely different histories.
4caac23f66 ... c009c65c45

3 changed files with 18 additions and 72 deletions
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13
src/frames.rs
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@ -1,11 +1,9 @@
use std::{thread, time};
use std::time::Instant;
pub struct Frames {
count: usize,
timer: Instant,
time_start: u128,
fps: u128,
}
impl Frames {
@ -14,7 +12,6 @@ impl Frames {
count: 0,
timer: Instant::now(),
time_start: 0,
fps: 1000 / 63,
}
}
@ -37,14 +34,4 @@ impl Frames {
pub fn count(&self) -> usize {
self.count
}
pub fn limit(&mut self) {
let elapsed = self.elapsed_ms();
// println!("{}", elapsed);
if elapsed > self.fps {
// println!("Frame dropped");
return;
}
thread::sleep(time::Duration::from_millis((self.fps - elapsed).try_into().unwrap()));
}
}

7
src/render.rs
View File

@ -43,7 +43,6 @@ pub fn create_window<T>(width: u32, height: u32, title: String, event_loop: &Eve
pub fn start_eventloop() {
let mut emulator = Emulator::new();
let mut frames = Frames::new();
let mut frame_limit = Frames::new();
env_logger::init();
let event_loop = EventLoop::new();
@ -81,16 +80,16 @@ pub fn start_eventloop() {
*control_flow = ControlFlow::Exit
},
Event::MainEventsCleared => {
frame_limit.reset_timer();
emulator.run(Cycles(70224), pixels.get_frame());
frames.increment();
window.request_redraw();
if frames.elapsed_ms() >= 1000 {
window.set_title(&format!("rmg-001 (FPS: {})", frames.count()));
frames.reset_count();
frames.reset_timer();
}
frame_limit.limit();
// thread::sleep(time::Duration::from_millis(1));
window.request_redraw();
},
Event::RedrawRequested(_) => {
if pixels

70
src/rom.rs
View File

@ -568,9 +568,6 @@ pub struct MBC3 {
rom_bank: u16,
ram_bank: u8,
ram_timer_enable: bool,
map_rtc: bool,
prev_rtc_latch: u8,
rtc_register: u8,
}
impl MBC3 {
@ -589,24 +586,17 @@ impl MBC3 {
rom_bank: 1,
ram_bank: 0,
ram_timer_enable: false,
map_rtc: false,
prev_rtc_latch: 0,
rtc_register: 0x08,
}
}
fn switch_rom_bank(&mut self, bank: u16) {
self.rom_bank = bank & 0b01111111;
self.rom_bank = bank;
if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
self.rom_bank = self.info.rom_banks.saturating_sub(1);
} else if self.rom_bank == 0 {
self.rom_bank = 1;
}
}
fn get_ram_address(&self, address: u16) -> usize {
(0x2000 * self.ram_bank as usize) + (address as usize - 0xA000)
}
}
impl ROM for MBC3 {
@ -614,32 +604,25 @@ impl ROM for MBC3 {
if BANK_ZERO.contains(&address) {
return self.data[address as usize];
} else if BANK_SWITCHABLE.contains(&address) {
return self.data[((self.rom_bank as usize * 0x4000) + (address as usize - 0x4000)) as usize];
return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
} else if EXTERNAL_RAM.contains(&address) {
if self.map_rtc {
if !self.ram_timer_enable {
return 0xFF;
}
if !self.info.has_ram || !self.ram_timer_enable {
return 0xFF;
} else {
if !self.ram_timer_enable {
return 0xFF;
}
let address = self.get_ram_address(address);
return match self.ram.get(address) {
Some(data) => *data,
None => 0xFF,
};
}
return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
Some(data) => *data,
None => 0xFF,
};
}
unreachable!("Invalid ROM read: {}", address);
return 0xFF;
}
fn write(&mut self, address: u16, data: u8) {
if address <= 0x1FFF {
if address >= 0xA000 && address <= 0xBFFF {
} else if address <= 0x1FFF {
match data {
0x0A => self.ram_timer_enable = true,
0x00 => self.ram_timer_enable = false,
0x00 => self.ram_timer_enable = true,
_ => {},
}
} else if address >= 0x2000 && address <= 0x3FFF {
@ -647,29 +630,11 @@ impl ROM for MBC3 {
} else if address >= 0x4000 && address <= 0x5FFF {
if data <= 0x03 {
self.ram_bank = data;
self.map_rtc = false;
} else if data >= 0x08 && data <= 0x0C {
self.rtc_register = data;
self.map_rtc = true;
} else if data >= 0x08 && data <= 0x0C && self.info.has_timer {
}
} else if address >= 0x6000 && address <= 0x7FFF {
if self.prev_rtc_latch == 0 && data == 1 {
// latch
}
self.prev_rtc_latch = data;
} else if address >= 0xA000 && address <= 0xBFFF {
if !self.ram_timer_enable {
return;
}
if self.map_rtc {
} else {
let address = self.get_ram_address(address);
if let Some(elem) = self.ram.get_mut(address) {
*elem = data;
}
}
}
}
fn ram_mut(&mut self) -> &mut Vec<u8> {
@ -712,10 +677,6 @@ impl MBC5 {
ram_enable: false,
}
}
fn get_ram_address(&self, address: u16) -> usize {
(0x2000 * self.ram_bank as usize) + (address as usize - 0xA000)
}
}
impl ROM for MBC5 {
@ -731,7 +692,7 @@ impl ROM for MBC5 {
if !self.info.has_ram || !self.ram_enable {
return 0xFF;
}
return match self.ram.get(self.get_ram_address(address)) {
return match self.ram.get(((self.ram_bank as usize * 0x2000) + (address as usize - 0x2000)) as usize) {
Some(data) => *data,
None => 0xFF,
};
@ -752,8 +713,7 @@ impl ROM for MBC5 {
if !self.ram_enable || !self.info.has_ram {
return;
}
let address = self.get_ram_address(address);
if let Some(elem) = self.ram.get_mut(address) {
if let Some(elem) = self.ram.get_mut(((self.ram_bank as usize * 0x2000) + (address as usize % 0x2000)) as usize) {
*elem = data;
}
}