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No commits in common. "806a4bf2116618ff890a574cd40a717a9500d153" and "aed56708fdcd0c6e50a1e1b4b26ff4f6e0cbe240" have entirely different histories.

6 changed files with 67 additions and 89 deletions

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@ -54,15 +54,14 @@ pub const INTERRUPT_FLAG_ADDRESS: u16 = 0xFF0F;
pub struct Bus { pub struct Bus {
game_rom: ROM, game_rom: ROM,
data: [u8; 0x10000], data: [u8; 0x10000],
pub reset_timer: bool,
} }
impl Bus { impl Bus {
pub fn new() -> Self { pub fn new() -> Self {
// let game_rom = match ROM::load_file("ignore/dr-mario.gb".to_string()) { let game_rom = match ROM::load_file("ignore/tetris.gb".to_string()) {
// let game_rom = match ROM::load_file("roms/cpu_instrs.gb".to_string()) { // let game_rom = match ROM::load_file("roms/cpu_instrs.gb".to_string()) {
// let game_rom = match ROM::load_file("roms/cpu_instrs_individual/01-special.gb".to_string()) { // let game_rom = match ROM::load_file("roms/cpu_instrs_individual/01-special.gb".to_string()) {
let game_rom = match ROM::load_file("roms/cpu_instrs_individual/02-interrupts.gb".to_string()) { // let game_rom = match ROM::load_file("roms/cpu_instrs_individual/02-interrupts.gb".to_string()) {
// let game_rom = match ROM::load_file("roms/cpu_instrs_individual/03-op sp,hl.gb".to_string()) { // let game_rom = match ROM::load_file("roms/cpu_instrs_individual/03-op sp,hl.gb".to_string()) {
// let game_rom = match ROM::load_file("roms/cpu_instrs_individual/04-op r,imm.gb".to_string()) { // let game_rom = match ROM::load_file("roms/cpu_instrs_individual/04-op r,imm.gb".to_string()) {
// let game_rom = match ROM::load_file("roms/cpu_instrs_individual/05-op rp.gb".to_string()) { // let game_rom = match ROM::load_file("roms/cpu_instrs_individual/05-op rp.gb".to_string()) {
@ -77,7 +76,6 @@ impl Bus {
_ => panic!("Could not read ROM"), _ => panic!("Could not read ROM"),
}; };
let mut data = [0x00; 0x10000]; let mut data = [0x00; 0x10000];
data[0xFF00] = 0b11001111;
data[0xFF01] = 0x00; data[0xFF01] = 0x00;
data[0xFF02] = 0x7E; data[0xFF02] = 0x7E;
data[0xFF04] = 0x18; data[0xFF04] = 0x18;
@ -97,12 +95,10 @@ impl Bus {
data[0xFF4A] = 0x00; data[0xFF4A] = 0x00;
data[0xFF4B] = 0x00; data[0xFF4B] = 0x00;
data[0xFFFF] = 0x00;
Self { Self {
data, data,
game_rom, game_rom,
reset_timer: false,
} }
} }
@ -122,10 +118,6 @@ impl Bus {
// print!("{}", data as char); // print!("{}", data as char);
} }
if address == 0xFF06 {
println!("Writing {:02X} to modulo", data);
}
if BANK_ZERO.in_range(address) || BANK_SWITCHABLE.in_range(address) { if BANK_ZERO.in_range(address) || BANK_SWITCHABLE.in_range(address) {
// println!("WRITING TO ROM"); // println!("WRITING TO ROM");
} else if WORK_RAM_1.in_range(address) || WORK_RAM_2.in_range(address) { } else if WORK_RAM_1.in_range(address) || WORK_RAM_2.in_range(address) {
@ -138,14 +130,13 @@ impl Bus {
self.data[address as usize] = data; self.data[address as usize] = data;
self.data[(WORK_RAM_1.begin() + (address - ECHO_RAM.begin())) as usize] = data; // Copy to the working RAM self.data[(WORK_RAM_1.begin() + (address - ECHO_RAM.begin())) as usize] = data; // Copy to the working RAM
} else if address == TIMER_DIVIDER_REGISTER_ADDRESS { } else if address == TIMER_DIVIDER_REGISTER_ADDRESS {
println!("bus timer reset"); self.data[address as usize] = 0x00;
self.reset_timer = true;
} else if address == LCD_CONTROL_ADDRESS && get_bit(data, BitIndex::I7) { } else if address == LCD_CONTROL_ADDRESS && get_bit(data, BitIndex::I7) {
self.data[address as usize] = data; self.data[address as usize] = data;
self.data[LCD_Y_ADDRESS as usize] = 0x00; self.data[LCD_Y_ADDRESS as usize] = 0x00;
} else if address == JOYPAD_ADDRESS { } else if address == JOYPAD_ADDRESS {
let byte = self.data[JOYPAD_ADDRESS as usize]; let byte = self.data[JOYPAD_ADDRESS as usize];
self.data[JOYPAD_ADDRESS as usize] = (data & 0b11110000) | (byte & 0b00001111); self.data[JOYPAD_ADDRESS as usize] = (data & 0b00110000) | 0b11000000 | (byte & 0b00001111);
} else { } else {
self.data[address as usize] = data; self.data[address as usize] = data;
} }

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@ -843,7 +843,6 @@ pub struct CPU {
exec_calls_count: usize, exec_calls_count: usize,
is_halted: bool, is_halted: bool,
ime: bool, // Interrupt Master Enable ime: bool, // Interrupt Master Enable
ei_delay: bool,
} }
impl CPU { impl CPU {
@ -854,7 +853,6 @@ impl CPU {
last_op_cycles: Cycles(0), last_op_cycles: Cycles(0),
exec_calls_count: 0, exec_calls_count: 0,
is_halted: false, is_halted: false,
ei_delay: false,
ime: true, ime: true,
} }
} }
@ -911,16 +909,14 @@ impl CPU {
} }
pub fn handle_interrupt(&mut self, bus: &mut Bus, interrupt: Interrupt) { pub fn handle_interrupt(&mut self, bus: &mut Bus, interrupt: Interrupt) {
println!("Interrupt: {:?}", interrupt); bus.set_interrupt_enable(interrupt, false);
bus.set_interrupt_flag(interrupt, false); bus.set_interrupt_flag(interrupt, false);
self.ime = false; let vector = interrupt.get_vector();
self.exec(Opcode::CALL(OpcodeParameter::U16(interrupt.get_vector())), bus); self.exec(Opcode::CALL(OpcodeParameter::U16(vector)), bus);
println!("Interrupt: {:?}", interrupt);
} }
pub fn check_interrupts(&mut self, bus: &mut Bus) -> Option<Interrupt> { pub fn check_interrupts(&mut self, bus: &mut Bus) -> Option<Interrupt> {
/* println!("IE {:08b}", bus.read(INTERRUPT_ENABLE_ADDRESS));
println!("IF {:08b}", bus.read(INTERRUPT_FLAG_ADDRESS));
println!("---"); */
if !self.ime && !self.is_halted { if !self.ime && !self.is_halted {
return None; return None;
} }
@ -956,12 +952,6 @@ impl CPU {
} }
self.increment_cycles(cycles); self.increment_cycles(cycles);
self.exec(opcode, bus); self.exec(opcode, bus);
if self.ei_delay && !self.ime {
println!("EI delay");
self.ei_delay = false;
self.run(bus);
self.ime = true;
}
} else if self.is_halted { } else if self.is_halted {
self.increment_cycles(Cycles(1)); self.increment_cycles(Cycles(1));
} }
@ -1791,20 +1781,25 @@ impl CPU {
Opcode::EI => { Opcode::EI => {
println!("EI"); println!("EI");
self.registers.increment(Register::PC, 1); self.registers.increment(Register::PC, 1);
self.ei_delay = true; self.ime = true;
}, },
// Disable interrupts // Disable interrupts
Opcode::DI => { Opcode::DI => {
println!("DI");
self.registers.increment(Register::PC, 1); self.registers.increment(Register::PC, 1);
self.ime = false; self.ime = false;
}, },
// Same as enabling interrupts and then executing RET // Same as enabling interrupts and then executing RET
Opcode::RETI => { Opcode::RETI => {
println!("RETI");
let prev_pc = self.registers.get(Register::PC);
self.exec(Opcode::EI, bus);
self.exec(Opcode::RET(OpcodeParameter::NoParam), bus); self.exec(Opcode::RET(OpcodeParameter::NoParam), bus);
self.ime = true; self.registers.set(Register::PC, prev_pc.wrapping_add(1));
}, },
// Don't execute instructions until an interrupt is requested // Don't execute instructions until an interrupt is requested
Opcode::HALT => { Opcode::HALT => {
println!("HALT");
self.registers.increment(Register::PC, 1); self.registers.increment(Register::PC, 1);
self.is_halted = true; self.is_halted = true;
}, },
@ -1812,11 +1807,8 @@ impl CPU {
self.registers.increment(Register::PC, 2); self.registers.increment(Register::PC, 2);
}, },
Opcode::NOP => self.registers.increment(Register::PC, 1), Opcode::NOP => self.registers.increment(Register::PC, 1),
Opcode::IllegalInstruction => { Opcode::IllegalInstruction => {panic!("Illegal instruction");},
println!("Illegal instruction!"); _ => {panic!("Illegal instruction");},
self.registers.increment(Register::PC, 1);
},
_ => unreachable!(),
}; };
} }
} }

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@ -112,10 +112,6 @@ impl Emulator {
self.cpu.reset_cycles(); self.cpu.reset_cycles();
while self.cpu.get_cycles().0 <= cpu_cycles.0 { while self.cpu.get_cycles().0 <= cpu_cycles.0 {
self.cpu.run(&mut self.bus); self.cpu.run(&mut self.bus);
if self.bus.reset_timer {
self.bus.reset_timer = false;
self.timer.reset(&mut self.bus);
}
self.ppu.do_cycles(&mut self.bus, self.cpu.get_last_op_cycles()); self.ppu.do_cycles(&mut self.bus, self.cpu.get_last_op_cycles());
self.timer.do_cycles(&mut self.bus, self.cpu.get_last_op_cycles()); self.timer.do_cycles(&mut self.bus, self.cpu.get_last_op_cycles());
} }

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@ -73,7 +73,8 @@ impl Joypad {
let direction = !get_bit(byte, BitIndex::I4); let direction = !get_bit(byte, BitIndex::I4);
let action = !get_bit(byte, BitIndex::I5); let action = !get_bit(byte, BitIndex::I5);
let data = (byte & 0b11110000) | let data = 0b11000000 |
(byte & 0b00110000) |
( (
(!((direction && self.down) || (action && self.start)) as u8) << 3 (!((direction && self.down) || (action && self.start)) as u8) << 3
) | ( ) | (

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@ -163,19 +163,16 @@ impl PPU {
self.reset_cycles(); self.reset_cycles();
PPU::set_lcd_y(bus, PPU::get_lcd_y(bus).wrapping_add(1)); PPU::set_lcd_y(bus, PPU::get_lcd_y(bus).wrapping_add(1));
let lyc_compare = PPU::get_lcd_y(bus) == bus.read(LCD_Y_COMPARE_ADDRESS);
PPU::set_lcd_status(bus, LCDStatus::LYCFlag, lyc_compare);
if PPU::get_lcd_status(bus, LCDStatus::LYCInterrupt) && lyc_compare {
PPU::request_interrupt(bus, Interrupt::LCDSTAT);
}
// Frame completed // Frame completed
if PPU::get_lcd_y(bus) > 153 { if PPU::get_lcd_y(bus) > 153 {
PPU::set_lcd_y(bus, 0); PPU::set_lcd_y(bus, 0);
} }
PPU::check_lyc(bus);
}
}
fn check_lyc(bus: &mut Bus) {
let lyc_compare = PPU::get_lcd_y(bus) == bus.read(LCD_Y_COMPARE_ADDRESS);
if PPU::get_lcd_status(bus, LCDStatus::LYCInterrupt) && lyc_compare {
PPU::set_lcd_status(bus, LCDStatus::LYCFlag, lyc_compare);
PPU::request_interrupt(bus, Interrupt::LCDSTAT);
} }
} }
@ -338,17 +335,17 @@ impl PPU {
0b01 => (palette_byte >> 2) & 0b11, 0b01 => (palette_byte >> 2) & 0b11,
0b10 => (palette_byte >> 4) & 0b11, 0b10 => (palette_byte >> 4) & 0b11,
0b11 => (palette_byte >> 6) & 0b11, 0b11 => (palette_byte >> 6) & 0b11,
_ => unreachable!(), _ => 0b00,
} }
} }
fn get_pixel(two_bit_pixel: u8) -> Pixel { fn get_pixel(two_bit_pixel: u8) -> Pixel {
match two_bit_pixel { match two_bit_pixel {
0b00 => Pixel::White, 0x00 => Pixel::White,
0b01 => Pixel::Light, 0x01 => Pixel::Light,
0b10 => Pixel::Dark, 0x10 => Pixel::Dark,
0b11 => Pixel::Black, 0x11 => Pixel::Black,
_ => unreachable!(), _ => Pixel::Black,
} }
} }

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@ -11,23 +11,23 @@ pub const TIMER_MODULO_ADDRESS: u16 = 0xFF06;
pub const TIMER_CONTROL_ADDRESS: u16 = 0xFF07; pub const TIMER_CONTROL_ADDRESS: u16 = 0xFF07;
pub struct Timer { pub struct Timer {
divider: u16, cycles: Cycles,
prev_result: bool,
} }
impl Timer { impl Timer {
pub fn new() -> Self { pub fn new() -> Self {
Self { Self {
divider: 0, cycles: Cycles(0),
prev_result: false,
} }
} }
pub fn reset(&mut self, bus: &mut Bus) { fn increment_cycles(&mut self, cycles: Cycles) {
println!("timer reset"); self.cycles.0 += cycles.0;
self.divider = 0; }
bus.force_write(TIMER_DIVIDER_REGISTER_ADDRESS, 0);
fn reset_cycles(&mut self) {
self.cycles.0 = 0;
} }
pub fn do_cycles(&mut self, bus: &mut Bus, cycles: Cycles) { pub fn do_cycles(&mut self, bus: &mut Bus, cycles: Cycles) {
@ -39,37 +39,38 @@ impl Timer {
} }
fn cycle(&mut self, bus: &mut Bus) { fn cycle(&mut self, bus: &mut Bus) {
self.divider = self.divider.wrapping_add(1); let div = bus.read(TIMER_DIVIDER_REGISTER_ADDRESS);
bus.force_write(TIMER_DIVIDER_REGISTER_ADDRESS, self.divider.to_be_bytes()[0]); bus.write(TIMER_DIVIDER_REGISTER_ADDRESS, div.wrapping_add(1));
let result = Timer::is_timer_enabled(bus) && self.get_tima_rate(bus); if Timer::is_timer_enabled(bus) {
let tima = bus.read(TIMER_COUNTER_ADDRESS);
if self.prev_result && !result { let tima_rate = Timer::get_tima_rate(bus);
let tima = bus.read(TIMER_COUNTER_ADDRESS).wrapping_add(1); if self.cycles.0 >= tima_rate {
if tima == 0 { if tima.checked_add(1) == None {
bus.write(TIMER_COUNTER_ADDRESS, bus.read(TIMER_MODULO_ADDRESS)); bus.write(TIMER_COUNTER_ADDRESS, bus.read(TIMER_MODULO_ADDRESS));
bus.set_interrupt_flag(Interrupt::Timer, true); bus.set_interrupt_flag(Interrupt::Timer, false);
println!("Timer interrupt set");
} else { } else {
bus.write(TIMER_COUNTER_ADDRESS, tima); bus.write(TIMER_COUNTER_ADDRESS, tima.wrapping_add(1));
}
self.reset_cycles();
} }
} }
self.prev_result = result; self.increment_cycles(Cycles(1));
} }
fn is_timer_enabled(bus: &Bus) -> bool { fn is_timer_enabled(bus: &Bus) -> bool {
get_bit(bus.read(TIMER_CONTROL_ADDRESS), BitIndex::I2) get_bit(bus.read(TIMER_CONTROL_ADDRESS), BitIndex::I2)
} }
fn get_tima_rate(&self, bus: &Bus) -> bool { fn get_tima_rate(bus: &Bus) -> usize {
let clock_select = bus.read(TIMER_CONTROL_ADDRESS) & 0b0000_0011; let clock_select = bus.read(TIMER_CONTROL_ADDRESS) & 0b0000_0011;
match clock_select { match clock_select {
0b00 => ((self.divider >> 9) & 1) == 1, 0b00 => 16,
0b01 => ((self.divider >> 3) & 1) == 1, 0b01 => 64,
0b10 => ((self.divider >> 5) & 1) == 1, 0b10 => 256,
0b11 => ((self.divider >> 7) & 1) == 1, 0b11 => 1024,
_ => unreachable!(), _ => 1,
} }
} }
} }