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fb929a05a9
@ -14,9 +14,10 @@ Any help or suggestion is welcome!
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- [x] Render the pixels
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- [ ] MBC Implementations
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- [x] NoMBC
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- [x] MBC1
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- [x] MBC2
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- [ ] MBC1
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- [ ] MBC2
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- [ ] MBC3
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- [ ] MBC4
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- [ ] MBC5
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- [ ] MBC6
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- [ ] MBC7
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10
src/cpu.rs
10
src/cpu.rs
@ -257,8 +257,8 @@ impl OpcodeParameterBytes {
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let opcode = self.0;
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let two_byte_param = join_bytes(self.2, self.1);
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match opcode {
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0x06 => (Opcode::LD(OpcodeParameter::Register_U8(Register::B, self.1)), Cycles(2)),
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0x0E => (Opcode::LD(OpcodeParameter::Register_U8(Register::C, self.1)), Cycles(2)),
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0x06 => (Opcode::LD(OpcodeParameter::Register_U8(Register::B, self.1)), Cycles(1)),
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0x0E => (Opcode::LD(OpcodeParameter::Register_U8(Register::C, self.1)), Cycles(3)),
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0x16 => (Opcode::LD(OpcodeParameter::Register_U8(Register::D, self.1)), Cycles(2)),
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0x1E => (Opcode::LD(OpcodeParameter::Register_U8(Register::E, self.1)), Cycles(2)),
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0x26 => (Opcode::LD(OpcodeParameter::Register_U8(Register::H, self.1)), Cycles(2)),
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@ -500,7 +500,7 @@ impl OpcodeParameterBytes {
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0x1B => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::E))), Cycles(2)),
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0x1C => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::H))), Cycles(2)),
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0x1D => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::L))), Cycles(2)),
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0x1E => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::HL))), Cycles(4)),
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0x1E => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::HL))), Cycles(2)),
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0x1F => (Opcode::PrefixCB(Box::new(Opcode::RR(Register::A))), Cycles(2)),
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0x20 => (Opcode::PrefixCB(Box::new(Opcode::SLA(Register::B))), Cycles(2)),
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@ -740,7 +740,7 @@ impl OpcodeParameterBytes {
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0xD2 => (Opcode::JP(OpcodeParameter::FlagRegisterReset_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)),
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0xDA => (Opcode::JP(OpcodeParameter::FlagRegisterSet_U16(FlagRegister::Carry, two_byte_param)), Cycles(3)),
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0xE9 => (Opcode::JP(OpcodeParameter::Register(Register::HL)), Cycles(1)),
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0x18 => (Opcode::JR(OpcodeParameter::I8(self.1 as i8)), Cycles(2)),
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0x18 => (Opcode::JR(OpcodeParameter::I8(self.1 as i8)), Cycles(3)),
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0x20 => (Opcode::JR(OpcodeParameter::FlagRegisterReset_I8(FlagRegister::Zero, self.1 as i8)), Cycles(2)),
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0x28 => (Opcode::JR(OpcodeParameter::FlagRegisterSet_I8(FlagRegister::Zero, self.1 as i8)), Cycles(2)),
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0x30 => (Opcode::JR(OpcodeParameter::FlagRegisterReset_I8(FlagRegister::Carry, self.1 as i8)), Cycles(2)),
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@ -909,7 +909,7 @@ impl CPU {
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}
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pub fn handle_interrupt(&mut self, bus: &mut Bus, interrupt: Interrupt) {
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println!("Interrupt: {:?}", interrupt);
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// println!("Interrupt: {:?}", interrupt);
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bus.set_interrupt_flag(interrupt, false);
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self.ime = false;
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self.registers.decrement(Register::PC, 3);
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152
src/rom.rs
152
src/rom.rs
@ -63,8 +63,6 @@ pub fn load_rom(filename: &str) -> std::io::Result<Box<dyn ROM>> {
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Ok(match info.mbc {
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MBC::NoMBC => Box::new(NoMBC::new(data, info)),
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MBC::MBC1 => Box::new(MBC1::new(data, info)),
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MBC::MBC2 => Box::new(MBC2::new(data, info)),
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MBC::MBC3 => Box::new(MBC3::new(data, info)),
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_ => unimplemented!(),
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})
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}
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@ -266,7 +264,8 @@ impl MBC1 {
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self.rom_bank = bank;
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if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
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self.rom_bank = self.info.rom_banks.saturating_sub(1);
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} else if self.rom_bank == 0 {
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}
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if self.rom_bank == 0 {
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self.rom_bank = 1;
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}
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}
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@ -324,150 +323,3 @@ impl ROM for MBC1 {
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}
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}
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}
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pub struct MBC2 {
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data: Vec<u8>,
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info: ROMInfo,
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ram: Vec<u8>,
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rom_bank: u16,
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ram_bank: u8,
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ram_enable: bool,
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}
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impl MBC2 {
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fn new(data: Vec<u8>, info: ROMInfo) -> Self {
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println!("MBC {:?}", info.mbc);
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println!("Region {:?}", info.region);
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println!("Has RAM {}", info.has_ram);
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println!("ROM banks {}", info.rom_banks);
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println!("RAM banks {}", info.ram_banks);
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let ram = Vec::with_capacity(info.ram_size() as usize);
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Self {
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data,
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info,
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ram,
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rom_bank: 1,
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ram_bank: 0,
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ram_enable: false,
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}
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}
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fn switch_rom_bank(&mut self, bank: u16) {
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self.rom_bank = bank;
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if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
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self.rom_bank = self.info.rom_banks.saturating_sub(1);
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} else if self.rom_bank == 0 {
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self.rom_bank = 1;
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}
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}
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}
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impl ROM for MBC2 {
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fn read(&self, address: u16) -> u8 {
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if BANK_ZERO.contains(&address) {
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return self.data[address as usize];
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} else if BANK_SWITCHABLE.contains(&address) {
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return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
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} else if address >= 0xA000 && address <= 0xA1FF {
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if !self.info.has_ram || !self.ram_enable {
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return 0xFF;
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}
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return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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} else if address >= 0xA200 && address <= 0xBFFF {
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return self.read(0xA000 + (address % 0x0200));
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}
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return 0xFF;
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}
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fn write(&mut self, address: u16, data: u8) {
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if BANK_SWITCHABLE.contains(&address) {
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if address.to_be_bytes()[0] & 1 == 0 {
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match data {
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0x0A => self.ram_enable = true,
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_ => self.ram_enable = false,
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}
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} else {
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self.switch_rom_bank(data as u16);
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}
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}
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}
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}
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pub struct MBC3 {
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data: Vec<u8>,
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info: ROMInfo,
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ram: Vec<u8>,
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rom_bank: u16,
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ram_bank: u8,
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ram_timer_enable: bool,
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}
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impl MBC3 {
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fn new(data: Vec<u8>, info: ROMInfo) -> Self {
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println!("MBC {:?}", info.mbc);
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println!("Region {:?}", info.region);
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println!("Has RAM {}", info.has_ram);
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println!("ROM banks {}", info.rom_banks);
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println!("RAM banks {}", info.ram_banks);
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let ram = Vec::with_capacity(info.ram_size() as usize);
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Self {
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data,
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info,
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ram,
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rom_bank: 1,
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ram_bank: 0,
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ram_timer_enable: false,
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}
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}
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fn switch_rom_bank(&mut self, bank: u16) {
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self.rom_bank = bank;
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if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
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self.rom_bank = self.info.rom_banks.saturating_sub(1);
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} else if self.rom_bank == 0 {
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self.rom_bank = 1;
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}
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}
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}
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impl ROM for MBC3 {
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fn read(&self, address: u16) -> u8 {
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if BANK_ZERO.contains(&address) {
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return self.data[address as usize];
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} else if BANK_SWITCHABLE.contains(&address) {
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return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.info.has_ram || !self.ram_timer_enable {
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return 0xFF;
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}
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return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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}
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return 0xFF;
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}
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fn write(&mut self, address: u16, data: u8) {
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if address >= 0xA000 && address <= 0xBFFF {
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} else if address <= 0x1FFF {
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match data {
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0x0A => self.ram_timer_enable = true,
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0x00 => self.ram_timer_enable = true,
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_ => {},
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}
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} else if address >= 0x2000 && address <= 0x3FFF {
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self.switch_rom_bank(data as u16);
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} else if address >= 0x4000 && address <= 0x5FFF {
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if data <= 0x03 {
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self.ram_bank = data;
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} else if data >= 0x08 && data <= 0x0C && self.info.has_timer {
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}
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} else if address >= 0x6000 && address <= 0x7FFF {
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}
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}
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}
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