FranLMSP/rmg-001
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compare: FranLMSP:6104f5b077ddcedd79bd52fc5e4ea861b80d9511
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FranLMSP:main

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2 changed files with 114 additions and 181 deletions
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61
src/bus.rs
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@ -2,7 +2,7 @@ use std::ops::RangeInclusive;
use crate::utils::{ use crate::utils::{
join_bytes join_bytes
}; };
use crate::rom::{ROM, load_rom}; use crate::rom::ROM;
use crate::ppu::{ use crate::ppu::{
PPU, PPU,
DMA_ADDRESS, DMA_ADDRESS,
@ -27,7 +27,7 @@ pub const INTERRUPT_ENABLE_ADDRESS: u16 = 0xFFFF;
pub const INTERRUPT_FLAG_ADDRESS: u16 = 0xFF0F; pub const INTERRUPT_FLAG_ADDRESS: u16 = 0xFF0F;
pub struct Bus { pub struct Bus {
game_rom: Box<dyn ROM>, game_rom: ROM,
data: [u8; 0x10000], data: [u8; 0x10000],
pub ppu: PPU, pub ppu: PPU,
pub joypad: Joypad, pub joypad: Joypad,
@ -41,45 +41,44 @@ impl Bus {
println!("Please, specify a ROM file"); println!("Please, specify a ROM file");
std::process::exit(1); std::process::exit(1);
} }
let game_rom = match load_rom(&args[1]) { let game_rom = match ROM::load_file(&args[1]) {
Ok(rom) => rom, Ok(rom) => rom,
Err(err) => { Err(err) => {
println!("Could not read ROM: {}", err); println!("Could not read ROM: {}", err);
std::process::exit(1); std::process::exit(1);
}, },
}; };
let mut bus = Self { let mut data = [0x00; 0x10000];
data: [0x00; 0x10000], // Hardware registers after the bootrom
data[0xFF00] = 0xCF;
data[0xFF01] = 0x00;
data[0xFF02] = 0x7E;
data[0xFF04] = 0x18;
data[0xFF05] = 0x00;
data[0xFF06] = 0x00;
data[0xFF07] = 0xF8;
data[0xFF0F] = 0xE1;
data[0xFF40] = 0x91;
data[0xFF41] = 0x81;
data[0xFF42] = 0x00;
data[0xFF43] = 0x00;
data[0xFF44] = 0x91;
data[0xFF45] = 0x00;
data[0xFF46] = 0xFF;
data[0xFF47] = 0xFC;
data[0xFF4A] = 0x00;
data[0xFF4B] = 0x00;
data[0xFFFF] = 0x00;
Self {
data,
game_rom, game_rom,
ppu: PPU::new(), ppu: PPU::new(),
joypad: Joypad::new(), joypad: Joypad::new(),
timer: Timer::new(), timer: Timer::new(),
}; }
// Hardware registers after the bootrom
bus.write(0xFF00, 0xCF);
bus.write(0xFF01, 0x00);
bus.write(0xFF02, 0x7E);
bus.write(0xFF04, 0x18);
bus.write(0xFF05, 0x00);
bus.write(0xFF06, 0x00);
bus.write(0xFF07, 0xF8);
bus.write(0xFF0F, 0xE1);
bus.write(0xFF40, 0x91);
bus.write(0xFF41, 0x81);
bus.write(0xFF42, 0x00);
bus.write(0xFF43, 0x00);
bus.write(0xFF44, 0x91);
bus.write(0xFF45, 0x00);
bus.write(0xFF46, 0xFF);
bus.write(0xFF47, 0xFC);
bus.write(0xFF4A, 0x00);
bus.write(0xFF4B, 0x00);
bus.write(0xFFFF, 0x00);
bus
} }
pub fn read(&self, address: u16) -> u8 { pub fn read(&self, address: u16) -> u8 {

156
src/rom.rs
View File

@ -1,6 +1,4 @@
#[cfg(not(test))]
use std::fs::File; use std::fs::File;
#[cfg(not(test))]
use std::io::Read; use std::io::Read;
use crate::bus::{ use crate::bus::{
@ -15,56 +13,11 @@ pub const SGB_FLAG_ADDRESS: u16 = 0x0146;
pub const RAM_SIZE_ADDRESS: u16 = 0x0149; pub const RAM_SIZE_ADDRESS: u16 = 0x0149;
pub const ROM_SIZE_ADDRESS: u16 = 0x0148; pub const ROM_SIZE_ADDRESS: u16 = 0x0148;
pub const DESTINATION_CODE_ADDRESS: u16 = 0x014A; pub const DESTINATION_CODE_ADDRESS: u16 = 0x014A;
pub const HEADER_CHECKSUM_ADDRESS: u16 = 0x014D;
#[cfg(not(test))] #[derive(Debug)]
fn header_checksum(data: &Vec<u8>) -> bool { enum Region {
if data.len() < HEADER_CHECKSUM_ADDRESS as usize { Japanese,
return false; NonJapanese,
}
let mut checksum: u8 = 0;
let mut index: u16 = 0x0134;
while index < HEADER_CHECKSUM_ADDRESS {
checksum = checksum.wrapping_sub(data[index as usize]).wrapping_sub(1);
index += 1;
}
checksum == data[HEADER_CHECKSUM_ADDRESS as usize]
}
#[cfg(test)]
pub fn load_rom(_filename: &str) -> std::io::Result<Box<dyn ROM>> {
Ok(Box::new(NoMBC::new(Vec::new(), ROMInfo {
mbc: MBC::NoMBC,
publisher: "".to_string(),
title: "".to_string(),
cgb_only: false,
sgb_features: false,
has_ram: false,
has_battery: false,
has_timer: false,
ram_banks: 0,
rom_banks: 2,
region: Region::NonJapanese,
})))
}
#[cfg(not(test))]
pub fn load_rom(filename: &str) -> std::io::Result<Box<dyn ROM>> {
let mut file = File::open(filename)?;
let mut data = vec![];
file.read_to_end(&mut data)?;
if !header_checksum(&data) {
return Err(std::io::Error::new(std::io::ErrorKind::InvalidData, "Header checksum failed. Is this a Gameboy ROM?"));
}
let info = ROMInfo::from_bytes(&data);
Ok(match info.mbc {
MBC::NoMBC => Box::new(NoMBC::new(data, info)),
MBC::MBC1 => Box::new(MBC1::new(data, info)),
_ => unimplemented!(),
})
} }
#[derive(Debug, Copy, Clone)] #[derive(Debug, Copy, Clone)]
@ -83,12 +36,6 @@ enum MBC {
BandaiTIMA5, BandaiTIMA5,
} }
#[derive(Debug)]
enum Region {
Japanese,
NonJapanese,
}
#[derive(Debug)] #[derive(Debug)]
enum BankingMode { enum BankingMode {
Simple, Simple,
@ -197,41 +144,7 @@ impl ROMInfo {
} }
} }
pub trait ROM { pub struct ROM {
fn read(&self, address: u16) -> u8;
fn write(&mut self, address: u16, data: u8);
}
pub struct NoMBC {
data: Vec<u8>,
info: ROMInfo,
}
impl NoMBC {
pub fn new(data: Vec<u8>, info: ROMInfo) -> Self {
let rom = Self {
data,
info,
};
println!("MBC {:?}", rom.info.mbc);
println!("Region {:?}", rom.info.region);
rom
}
}
impl ROM for NoMBC {
fn read(&self, address: u16) -> u8 {
match self.data.get(address as usize) {
Some(byte) => *byte,
None => 0xFF,
}
}
fn write(&mut self, _address: u16, _data: u8) {}
}
pub struct MBC1 {
data: Vec<u8>, data: Vec<u8>,
info: ROMInfo, info: ROMInfo,
ram: Vec<u8>, ram: Vec<u8>,
@ -241,15 +154,21 @@ pub struct MBC1 {
banking_mode: BankingMode, banking_mode: BankingMode,
} }
impl MBC1 { impl ROM {
fn new(data: Vec<u8>, info: ROMInfo) -> Self { pub fn load_file(filename: &str) -> std::io::Result<Self> {
let mut file = File::open(filename)?;
let mut data = vec![];
file.read_to_end(&mut data)?;
let info = ROMInfo::from_bytes(&data);
println!("MBC {:?}", info.mbc); println!("MBC {:?}", info.mbc);
println!("Region {:?}", info.region);
println!("Has RAM {}", info.has_ram); println!("Has RAM {}", info.has_ram);
println!("ROM banks {}", info.rom_banks); println!("ROM banks {}", info.rom_banks);
println!("RAM banks {}", info.ram_banks); println!("RAM banks {}", info.ram_banks);
println!("Region {:?}", info.region);
let ram = Vec::with_capacity(info.ram_size() as usize); let ram = Vec::with_capacity(info.ram_size() as usize);
Self {
Ok(Self {
data, data,
info, info,
ram, ram,
@ -257,22 +176,18 @@ impl MBC1 {
ram_bank: 0, ram_bank: 0,
ram_enable: false, ram_enable: false,
banking_mode: BankingMode::Simple, banking_mode: BankingMode::Simple,
} })
} }
fn switch_rom_bank(&mut self, bank: u16) { pub fn read(&self, address: u16) -> u8 {
self.rom_bank = bank; match self.info.mbc {
if self.rom_bank > self.info.rom_banks.saturating_sub(1) { MBC::NoMBC => {
self.rom_bank = self.info.rom_banks.saturating_sub(1); return match self.data.get(address as usize) {
} Some(data) => *data,
if self.rom_bank == 0 { None => 0xFF,
self.rom_bank = 1; };
} },
} MBC::MBC1 => {
}
impl ROM for MBC1 {
fn read(&self, address: u16) -> u8 {
if BANK_ZERO.contains(&address) { if BANK_ZERO.contains(&address) {
return self.data[address as usize]; return self.data[address as usize];
} else if BANK_SWITCHABLE.contains(&address) { } else if BANK_SWITCHABLE.contains(&address) {
@ -287,9 +202,15 @@ impl ROM for MBC1 {
}; };
} }
unreachable!("ROM read: Address {} not valid", address); unreachable!("ROM read: Address {} not valid", address);
},
_ => unimplemented!(),
}
} }
fn write(&mut self, address: u16, data: u8) { pub fn write(&mut self, address: u16, data: u8) {
match self.info.mbc {
MBC::NoMBC => {},
MBC::MBC1 => {
if address <= 0x1FFF { // RAM enable register if address <= 0x1FFF { // RAM enable register
if !self.info.has_ram { if !self.info.has_ram {
return; return;
@ -321,5 +242,18 @@ impl ROM for MBC1 {
} }
self.switch_rom_bank(self.rom_bank + (data as u16 >> 5)); self.switch_rom_bank(self.rom_bank + (data as u16 >> 5));
} }
},
_ => unimplemented!(),
}
}
pub fn switch_rom_bank(&mut self, bank: u16) {
self.rom_bank = bank;
if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
self.rom_bank = self.info.rom_banks.saturating_sub(1);
}
if self.rom_bank == 0 {
self.rom_bank = 1;
}
} }
} }