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https://github.com/FranLMSP/rmg-001.git
synced 2024-11-10 12:11:32 +00:00
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No commits in common. "fb929a05a95ba64ed500574d429fe38268f29867" and "6104f5b077ddcedd79bd52fc5e4ea861b80d9511" have entirely different histories.
fb929a05a9
...
6104f5b077
61
src/bus.rs
61
src/bus.rs
@ -2,7 +2,7 @@ use std::ops::RangeInclusive;
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use crate::utils::{
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join_bytes
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};
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use crate::rom::{ROM, load_rom};
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use crate::rom::ROM;
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use crate::ppu::{
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PPU,
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DMA_ADDRESS,
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@ -27,7 +27,7 @@ pub const INTERRUPT_ENABLE_ADDRESS: u16 = 0xFFFF;
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pub const INTERRUPT_FLAG_ADDRESS: u16 = 0xFF0F;
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pub struct Bus {
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game_rom: Box<dyn ROM>,
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game_rom: ROM,
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data: [u8; 0x10000],
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pub ppu: PPU,
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pub joypad: Joypad,
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@ -41,45 +41,44 @@ impl Bus {
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println!("Please, specify a ROM file");
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std::process::exit(1);
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}
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let game_rom = match load_rom(&args[1]) {
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let game_rom = match ROM::load_file(&args[1]) {
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Ok(rom) => rom,
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Err(err) => {
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println!("Could not read ROM: {}", err);
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std::process::exit(1);
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},
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};
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let mut bus = Self {
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data: [0x00; 0x10000],
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let mut data = [0x00; 0x10000];
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// Hardware registers after the bootrom
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data[0xFF00] = 0xCF;
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data[0xFF01] = 0x00;
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data[0xFF02] = 0x7E;
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data[0xFF04] = 0x18;
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data[0xFF05] = 0x00;
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data[0xFF06] = 0x00;
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data[0xFF07] = 0xF8;
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data[0xFF0F] = 0xE1;
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data[0xFF40] = 0x91;
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data[0xFF41] = 0x81;
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data[0xFF42] = 0x00;
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data[0xFF43] = 0x00;
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data[0xFF44] = 0x91;
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data[0xFF45] = 0x00;
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data[0xFF46] = 0xFF;
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data[0xFF47] = 0xFC;
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data[0xFF4A] = 0x00;
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data[0xFF4B] = 0x00;
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data[0xFFFF] = 0x00;
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Self {
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data,
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game_rom,
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ppu: PPU::new(),
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joypad: Joypad::new(),
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timer: Timer::new(),
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};
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// Hardware registers after the bootrom
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bus.write(0xFF00, 0xCF);
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bus.write(0xFF01, 0x00);
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bus.write(0xFF02, 0x7E);
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bus.write(0xFF04, 0x18);
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bus.write(0xFF05, 0x00);
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bus.write(0xFF06, 0x00);
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bus.write(0xFF07, 0xF8);
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bus.write(0xFF0F, 0xE1);
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bus.write(0xFF40, 0x91);
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bus.write(0xFF41, 0x81);
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bus.write(0xFF42, 0x00);
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bus.write(0xFF43, 0x00);
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bus.write(0xFF44, 0x91);
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bus.write(0xFF45, 0x00);
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bus.write(0xFF46, 0xFF);
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bus.write(0xFF47, 0xFC);
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bus.write(0xFF4A, 0x00);
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bus.write(0xFF4B, 0x00);
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bus.write(0xFFFF, 0x00);
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bus
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}
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}
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pub fn read(&self, address: u16) -> u8 {
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234
src/rom.rs
234
src/rom.rs
@ -1,6 +1,4 @@
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#[cfg(not(test))]
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use std::fs::File;
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#[cfg(not(test))]
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use std::io::Read;
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use crate::bus::{
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@ -15,56 +13,11 @@ pub const SGB_FLAG_ADDRESS: u16 = 0x0146;
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pub const RAM_SIZE_ADDRESS: u16 = 0x0149;
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pub const ROM_SIZE_ADDRESS: u16 = 0x0148;
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pub const DESTINATION_CODE_ADDRESS: u16 = 0x014A;
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pub const HEADER_CHECKSUM_ADDRESS: u16 = 0x014D;
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#[cfg(not(test))]
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fn header_checksum(data: &Vec<u8>) -> bool {
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if data.len() < HEADER_CHECKSUM_ADDRESS as usize {
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return false;
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}
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let mut checksum: u8 = 0;
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let mut index: u16 = 0x0134;
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while index < HEADER_CHECKSUM_ADDRESS {
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checksum = checksum.wrapping_sub(data[index as usize]).wrapping_sub(1);
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index += 1;
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}
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checksum == data[HEADER_CHECKSUM_ADDRESS as usize]
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}
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#[cfg(test)]
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pub fn load_rom(_filename: &str) -> std::io::Result<Box<dyn ROM>> {
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Ok(Box::new(NoMBC::new(Vec::new(), ROMInfo {
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mbc: MBC::NoMBC,
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publisher: "".to_string(),
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title: "".to_string(),
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cgb_only: false,
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sgb_features: false,
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has_ram: false,
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has_battery: false,
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has_timer: false,
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ram_banks: 0,
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rom_banks: 2,
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region: Region::NonJapanese,
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})))
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}
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#[cfg(not(test))]
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pub fn load_rom(filename: &str) -> std::io::Result<Box<dyn ROM>> {
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let mut file = File::open(filename)?;
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let mut data = vec![];
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file.read_to_end(&mut data)?;
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if !header_checksum(&data) {
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return Err(std::io::Error::new(std::io::ErrorKind::InvalidData, "Header checksum failed. Is this a Gameboy ROM?"));
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}
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let info = ROMInfo::from_bytes(&data);
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Ok(match info.mbc {
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MBC::NoMBC => Box::new(NoMBC::new(data, info)),
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MBC::MBC1 => Box::new(MBC1::new(data, info)),
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_ => unimplemented!(),
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})
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#[derive(Debug)]
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enum Region {
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Japanese,
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NonJapanese,
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}
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#[derive(Debug, Copy, Clone)]
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@ -83,12 +36,6 @@ enum MBC {
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BandaiTIMA5,
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}
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#[derive(Debug)]
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enum Region {
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Japanese,
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NonJapanese,
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}
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#[derive(Debug)]
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enum BankingMode {
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Simple,
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@ -197,41 +144,7 @@ impl ROMInfo {
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}
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}
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pub trait ROM {
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fn read(&self, address: u16) -> u8;
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fn write(&mut self, address: u16, data: u8);
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}
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pub struct NoMBC {
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data: Vec<u8>,
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info: ROMInfo,
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}
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impl NoMBC {
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pub fn new(data: Vec<u8>, info: ROMInfo) -> Self {
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let rom = Self {
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data,
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info,
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};
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println!("MBC {:?}", rom.info.mbc);
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println!("Region {:?}", rom.info.region);
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rom
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}
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}
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impl ROM for NoMBC {
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fn read(&self, address: u16) -> u8 {
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match self.data.get(address as usize) {
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Some(byte) => *byte,
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None => 0xFF,
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}
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}
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fn write(&mut self, _address: u16, _data: u8) {}
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}
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pub struct MBC1 {
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pub struct ROM {
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data: Vec<u8>,
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info: ROMInfo,
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ram: Vec<u8>,
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@ -241,15 +154,21 @@ pub struct MBC1 {
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banking_mode: BankingMode,
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}
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impl MBC1 {
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fn new(data: Vec<u8>, info: ROMInfo) -> Self {
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impl ROM {
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pub fn load_file(filename: &str) -> std::io::Result<Self> {
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let mut file = File::open(filename)?;
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let mut data = vec![];
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file.read_to_end(&mut data)?;
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let info = ROMInfo::from_bytes(&data);
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println!("MBC {:?}", info.mbc);
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println!("Region {:?}", info.region);
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println!("Has RAM {}", info.has_ram);
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println!("ROM banks {}", info.rom_banks);
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println!("RAM banks {}", info.ram_banks);
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println!("Region {:?}", info.region);
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let ram = Vec::with_capacity(info.ram_size() as usize);
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Self {
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Ok(Self {
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data,
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info,
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ram,
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@ -257,10 +176,78 @@ impl MBC1 {
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ram_bank: 0,
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ram_enable: false,
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banking_mode: BankingMode::Simple,
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})
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}
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pub fn read(&self, address: u16) -> u8 {
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match self.info.mbc {
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MBC::NoMBC => {
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return match self.data.get(address as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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},
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MBC::MBC1 => {
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if BANK_ZERO.contains(&address) {
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return self.data[address as usize];
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} else if BANK_SWITCHABLE.contains(&address) {
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return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.info.has_ram {
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return 0xFF;
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}
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return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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}
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unreachable!("ROM read: Address {} not valid", address);
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},
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_ => unimplemented!(),
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}
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}
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fn switch_rom_bank(&mut self, bank: u16) {
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pub fn write(&mut self, address: u16, data: u8) {
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match self.info.mbc {
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MBC::NoMBC => {},
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MBC::MBC1 => {
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if address <= 0x1FFF { // RAM enable register
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if !self.info.has_ram {
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return;
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}
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self.ram_enable = match data & 0x0F {
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0x0A => true,
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_ => false,
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};
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return;
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} else if address >= 0x2000 && address <= 0x3FFF { // ROM bank number register
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// println!("Switch bank to {:02X}", data);
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self.switch_rom_bank(data as u16 & 0b00011111);
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} else if address >= 0x4000 && address <= 0x5FFF { // ROM and RAM bank number register
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// println!("RAM bank {:02X}", data);
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self.ram_bank = data & 0b11;
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} else if address >= 0x6000 && address <= 0x7FFF { // Banking mode select
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self.banking_mode = match data & 1 {
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0 => BankingMode::Simple,
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1 => BankingMode::Advanced,
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_ => unreachable!(),
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}
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.ram_enable || !self.info.has_ram {
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return;
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}
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let address = address as usize - EXTERNAL_RAM.min().unwrap() as usize + (EXTERNAL_RAM.min().unwrap() as usize * self.ram_bank as usize);
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if let Some(elem) = self.ram.get_mut(address) {
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*elem = data;
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}
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self.switch_rom_bank(self.rom_bank + (data as u16 >> 5));
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}
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},
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_ => unimplemented!(),
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}
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}
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pub fn switch_rom_bank(&mut self, bank: u16) {
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self.rom_bank = bank;
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if self.rom_bank > self.info.rom_banks.saturating_sub(1) {
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self.rom_bank = self.info.rom_banks.saturating_sub(1);
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@ -270,56 +257,3 @@ impl MBC1 {
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}
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}
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}
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impl ROM for MBC1 {
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fn read(&self, address: u16) -> u8 {
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if BANK_ZERO.contains(&address) {
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return self.data[address as usize];
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} else if BANK_SWITCHABLE.contains(&address) {
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return self.data[((self.rom_bank as usize * 0x4000) + (address as usize & 0x3FFF)) as usize];
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.info.has_ram {
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return 0xFF;
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}
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return match self.ram.get((address - EXTERNAL_RAM.min().unwrap() + (0x2000 * self.ram_bank as u16)) as usize) {
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Some(data) => *data,
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None => 0xFF,
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};
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}
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unreachable!("ROM read: Address {} not valid", address);
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}
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fn write(&mut self, address: u16, data: u8) {
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if address <= 0x1FFF { // RAM enable register
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if !self.info.has_ram {
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return;
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}
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self.ram_enable = match data & 0x0F {
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0x0A => true,
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_ => false,
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};
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return;
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} else if address >= 0x2000 && address <= 0x3FFF { // ROM bank number register
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// println!("Switch bank to {:02X}", data);
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self.switch_rom_bank(data as u16 & 0b00011111);
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} else if address >= 0x4000 && address <= 0x5FFF { // ROM and RAM bank number register
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// println!("RAM bank {:02X}", data);
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self.ram_bank = data & 0b11;
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} else if address >= 0x6000 && address <= 0x7FFF { // Banking mode select
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self.banking_mode = match data & 1 {
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0 => BankingMode::Simple,
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1 => BankingMode::Advanced,
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_ => unreachable!(),
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}
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} else if EXTERNAL_RAM.contains(&address) {
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if !self.ram_enable || !self.info.has_ram {
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return;
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}
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let address = address as usize - EXTERNAL_RAM.min().unwrap() as usize + (EXTERNAL_RAM.min().unwrap() as usize * self.ram_bank as usize);
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if let Some(elem) = self.ram.get_mut(address) {
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*elem = data;
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}
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self.switch_rom_bank(self.rom_bank + (data as u16 >> 5));
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}
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}
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}
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Block a user