mirror of
https://github.com/FranLMSP/rmg-001.git
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74 lines
2.0 KiB
Rust
74 lines
2.0 KiB
Rust
use crate::cpu::{Interrupt, Cycles};
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use crate::bus::Bus;
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use crate::utils::{
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BitIndex,
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get_bit,
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};
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pub const TIMER_DIVIDER_REGISTER_ADDRESS: u16 = 0xFF04;
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pub const TIMER_COUNTER_ADDRESS: u16 = 0xFF05;
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pub const TIMER_MODULO_ADDRESS: u16 = 0xFF06;
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pub const TIMER_CONTROL_ADDRESS: u16 = 0xFF07;
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pub struct Timer {
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divider: u16,
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prev_result: bool,
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}
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impl Timer {
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pub fn new() -> Self {
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Self {
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divider: 0,
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prev_result: false,
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}
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}
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pub fn reset(&mut self, bus: &mut Bus) {
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self.divider = 0;
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bus.force_write(TIMER_DIVIDER_REGISTER_ADDRESS, 0);
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}
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pub fn do_cycles(&mut self, bus: &mut Bus, cycles: Cycles) {
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let mut count = 0;
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while count < cycles.to_t().0 {
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self.cycle(bus);
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count += 1;
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}
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}
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fn cycle(&mut self, bus: &mut Bus) {
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self.divider = self.divider.wrapping_add(1);
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bus.force_write(TIMER_DIVIDER_REGISTER_ADDRESS, self.divider.to_be_bytes()[0]);
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let result = Timer::is_timer_enabled(bus) && self.get_tima_rate(bus);
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if self.prev_result && !result {
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let tima = bus.read(TIMER_COUNTER_ADDRESS).wrapping_add(1);
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if tima == 0 {
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bus.write(TIMER_COUNTER_ADDRESS, bus.read(TIMER_MODULO_ADDRESS));
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bus.set_interrupt_flag(Interrupt::Timer, true);
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} else {
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bus.write(TIMER_COUNTER_ADDRESS, tima);
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}
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}
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self.prev_result = result;
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}
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fn is_timer_enabled(bus: &Bus) -> bool {
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get_bit(bus.read(TIMER_CONTROL_ADDRESS), BitIndex::I2)
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}
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fn get_tima_rate(&self, bus: &Bus) -> bool {
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let clock_select = bus.read(TIMER_CONTROL_ADDRESS) & 0b0000_0011;
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match clock_select {
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0b00 => ((self.divider >> 9) & 1) == 1,
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0b01 => ((self.divider >> 3) & 1) == 1,
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0b10 => ((self.divider >> 5) & 1) == 1,
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0b11 => ((self.divider >> 7) & 1) == 1,
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_ => unreachable!(),
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}
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}
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}
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