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clippy

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This commit is contained in:
Franco Colmenarez 2021-11-15 11:28:36 -05:00
parent 7fa6857ac3
commit 0aa6e56fc1
3 changed files with 3 additions and 8 deletions
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2
src/render.rs
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@ -3,8 +3,6 @@ use crate::frames::Frames;
use crate::cpu::{Cycles};
use crate::ppu::{WIDTH, HEIGHT};
use std::{thread, time};
use log::error;
use pixels::{wgpu, Pixels, PixelsBuilder, SurfaceTexture};
use winit::dpi::LogicalSize;

5
src/rom.rs
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@ -26,14 +26,12 @@ enum MBC {
MBC1,
MBC2,
MBC3,
MBC4,
MBC5,
MBC6,
MBC7,
HuC1,
HuC3,
MMM01,
MBC1M,
PocketCamera,
BandaiTIMA5,
}
@ -207,14 +205,13 @@ impl ROM {
},
_ => unimplemented!(),
}
self.data[address as usize]
}
pub fn write(&mut self, address: u16, data: u8) {
match self.info.mbc {
MBC::NoMBC => {},
MBC::MBC1 => {
if address >= 0x0000 && address <= 0x1FFF { // RAM enable register
if address <= 0x1FFF { // RAM enable register
if !self.info.has_ram {
return;
}

4
src/timer.rs
View File

@ -50,7 +50,7 @@ impl Timer {
fn cycle(&mut self, bus: &mut Bus) {
self.divider = self.divider.wrapping_add(1);
let result = self.is_enabled && self.get_tima_rate(bus);
let result = self.is_enabled && self.get_tima_rate();
if self.prev_result && !result {
let tima = bus.read(TIMER_COUNTER_ADDRESS).wrapping_add(1);
@ -69,7 +69,7 @@ impl Timer {
get_bit(bus.read(TIMER_CONTROL_ADDRESS), BitIndex::I2)
}
fn get_tima_rate(&self, bus: &Bus) -> bool {
fn get_tima_rate(&self) -> bool {
let clock_select = self.control & 0b0000_0011;
match clock_select {
0b00 => ((self.divider >> 9) & 1) == 1,