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Fix SRL instruction

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This commit is contained in:
Franco Colmenarez 2021-10-18 12:03:24 -05:00
parent 9b08306c96
commit 59acdd555e
1 changed files with 42 additions and 0 deletions
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42
src/cpu.rs
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@ -811,6 +811,22 @@ impl CPU {
self.registers.set_flag(FlagRegister::Substract, false); self.registers.set_flag(FlagRegister::Substract, false);
self.registers.set_flag(FlagRegister::HalfCarry, false); self.registers.set_flag(FlagRegister::HalfCarry, false);
}, },
Opcode::SRL(register) => {
let mut val = 0;
match register.is_8bit() {
true => val = self.registers.get_8bit(register),
false => val = bus.read(self.registers.get(register)),
};
let val = val >> 1;
match register.is_8bit() {
true => self.registers.set(register, val as u16),
false => bus.write(self.registers.get(register), val),
};
self.registers.set_flag(FlagRegister::Carry, get_bit(val, BitIndex::I0));
self.registers.set_flag(FlagRegister::Zero, val == 0);
self.registers.set_flag(FlagRegister::Substract, false);
self.registers.set_flag(FlagRegister::HalfCarry, false);
},
_ => {}, _ => {},
}; };
}, },
@ -2480,6 +2496,32 @@ mod tests {
assert_eq!(cpu.registers.get(Register::PC), 0x102); */ assert_eq!(cpu.registers.get(Register::PC), 0x102); */
} }
#[test]
fn test_prefix_cb_srl_instruction() {
let mut bus = Bus::new();
let mut cpu = CPU::new();
cpu.registers.set(Register::A, 0b00000010);
cpu.exec(Opcode::PrefixCB(Box::new(Opcode::SRL(Register::A))), &mut bus);
assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), true);
assert_eq!(cpu.registers.get(Register::A), 0b00000001);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
let mut cpu = CPU::new();
let addr = 0xC000;
bus.write(addr, 0b00000001);
cpu.registers.set(Register::HL, addr);
cpu.exec(Opcode::PrefixCB(Box::new(Opcode::SRL(Register::HL))), &mut bus);
assert_eq!(cpu.registers.get_flag(FlagRegister::Zero), true);
assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), false);
assert_eq!(cpu.registers.get_flag(FlagRegister::Carry), false);
assert_eq!(bus.read(addr), 0b00000000);
assert_eq!(cpu.registers.get(Register::PC), 0x102);
}
#[test] #[test]
fn test_nop_instructions() { fn test_nop_instructions() {
let mut cpu = CPU::new(); let mut cpu = CPU::new();