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CPL Instruction
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@ -2,7 +2,9 @@ use rust_boy::rom::ROM;
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use rust_boy::console::Console;
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use rust_boy::console::Console;
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fn main() -> std::io::Result<()> {
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fn main() -> std::io::Result<()> {
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let mut console = Console::new();
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/* let mut console = Console::new();
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console.cpu_run();
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console.cpu_run(); */
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let val: u8 = 0b11110000;
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println!("{:08b}", !val);
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Ok(())
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Ok(())
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}
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}
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20
src/cpu.rs
20
src/cpu.rs
@ -222,7 +222,7 @@ pub enum Opcode {
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LD(OpcodeParameter),
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LD(OpcodeParameter),
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LDD(OpcodeParameter),
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LDD(OpcodeParameter),
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LDI(OpcodeParameter),
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LDI(OpcodeParameter),
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LDHL(OpcodeParameter),
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// LDHL(OpcodeParameter),
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PUSH(Register),
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PUSH(Register),
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POP(Register),
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POP(Register),
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ADD(OpcodeParameter),
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ADD(OpcodeParameter),
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@ -1025,6 +1025,12 @@ impl CPU {
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_ => {},
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_ => {},
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};
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};
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},
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},
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Opcode::CPL => {
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self.registers.increment(Register::PC, 1);
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self.registers.set(Register::A, !self.registers.get(Register::A));
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self.registers.set_flag(FlagRegister::Substract, true);
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self.registers.set_flag(FlagRegister::HalfCarry, true);
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},
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// Disable interrupts
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// Disable interrupts
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Opcode::DI => {
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Opcode::DI => {
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bus.write(0xFFFF, 0x00); // Disable all interrupts
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bus.write(0xFFFF, 0x00); // Disable all interrupts
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@ -2987,6 +2993,18 @@ mod tests {
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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}
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}
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#[test]
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fn test_cpl_instructions() {
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let mut cpu = CPU::new();
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let mut bus = Bus::new();
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cpu.registers.set(Register::A, 0b11110000);
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cpu.exec(Opcode::CPL, &mut bus);
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assert_eq!(cpu.registers.get(Register::A), 0b00001111);
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assert_eq!(cpu.registers.get(Register::PC), 0x101);
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assert_eq!(cpu.registers.get_flag(FlagRegister::Substract), true);
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assert_eq!(cpu.registers.get_flag(FlagRegister::HalfCarry), true);
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}
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#[test]
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#[test]
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fn test_nop_instructions() {
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fn test_nop_instructions() {
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let mut cpu = CPU::new();
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let mut cpu = CPU::new();
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