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ADC and SBC instructions (no tests)
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parent
2b633c9ee0
commit
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42
src/cpu.rs
42
src/cpu.rs
@ -561,6 +561,27 @@ impl CPU {
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_ => {},
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};
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},
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Opcode::ADC(params) => match params {
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OpcodeParameter::Register_Register(reg1, reg2) => {
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if self.registers.get_flag(FlagRegister::Carry) {
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self.registers.increment(reg1, 1);
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}
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self.exec(Opcode::ADD(OpcodeParameter::Register_Register(reg1, reg2)), bus);
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},
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OpcodeParameter::Register_U8(reg1, val) => {
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if self.registers.get_flag(FlagRegister::Carry) {
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self.registers.increment(reg1, 1);
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}
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self.exec(Opcode::ADD(OpcodeParameter::Register_U8(reg1, val)), bus);
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},
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OpcodeParameter::Register_I8(reg1, val) => {
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if self.registers.get_flag(FlagRegister::Carry) {
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self.registers.increment(reg1, 1);
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}
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self.exec(Opcode::ADD(OpcodeParameter::Register_I8(reg1, val)), bus);
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},
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_ => {},
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},
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Opcode::SUB(params) => {
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self.registers.increment(Register::PC, 1);
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let mut register = Register::A;
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@ -595,6 +616,27 @@ impl CPU {
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self.registers.set_flag(FlagRegister::Carry, carry);
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self.registers.set_flag(FlagRegister::HalfCarry, sub_half_carry(val1.to_be_bytes()[1], val2.to_be_bytes()[1]));
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},
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Opcode::SBC(params) => match params {
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OpcodeParameter::Register_Register(reg1, reg2) => {
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if self.registers.get_flag(FlagRegister::Carry) {
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self.registers.decrement(reg1, 1);
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}
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self.exec(Opcode::SUB(OpcodeParameter::Register_Register(reg1, reg2)), bus);
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},
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OpcodeParameter::Register_U8(reg1, val) => {
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if self.registers.get_flag(FlagRegister::Carry) {
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self.registers.decrement(reg1, 1);
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}
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self.exec(Opcode::SUB(OpcodeParameter::Register_U8(reg1, val)), bus);
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},
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OpcodeParameter::Register_I8(reg1, val) => {
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if self.registers.get_flag(FlagRegister::Carry) {
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self.registers.decrement(reg1, 1);
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}
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self.exec(Opcode::SUB(OpcodeParameter::Register_I8(reg1, val)), bus);
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},
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_ => {},
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},
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// Increment by 1
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Opcode::INC(affect_flags, register) => {
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let prev_value = self.registers.get(register);
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@ -1,4 +1,4 @@
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#[derive(Debug)]
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#[derive(Debug, Copy, Clone)]
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pub enum BitIndex {
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I0,
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I1,
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