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Last interrupt instructions

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This commit is contained in:
Franco Colmenarez 2021-10-19 10:41:18 -05:00
parent ff9fd48190
commit b6b7e7bf73
1 changed files with 18 additions and 1 deletions
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19
src/cpu.rs
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@ -222,7 +222,7 @@ pub enum Opcode {
LD(OpcodeParameter), LD(OpcodeParameter),
LDD(OpcodeParameter), LDD(OpcodeParameter),
LDI(OpcodeParameter), LDI(OpcodeParameter),
// LDHL(OpcodeParameter), LDHL(OpcodeParameter),
PUSH(Register), PUSH(Register),
POP(Register), POP(Register),
ADD(OpcodeParameter), ADD(OpcodeParameter),
@ -1045,11 +1045,28 @@ impl CPU {
self.registers.set_flag(FlagRegister::Substract, false); self.registers.set_flag(FlagRegister::Substract, false);
self.registers.set_flag(FlagRegister::HalfCarry, false); self.registers.set_flag(FlagRegister::HalfCarry, false);
}, },
// Enable interrupts
Opcode::EI => {
self.registers.increment(Register::PC, 1);
bus.write(0xFFFF, 0xFF); // Disable all interrupts
},
// Disable interrupts // Disable interrupts
Opcode::DI => { Opcode::DI => {
self.registers.increment(Register::PC, 1); self.registers.increment(Register::PC, 1);
bus.write(0xFFFF, 0x00); // Disable all interrupts bus.write(0xFFFF, 0x00); // Disable all interrupts
}, },
// Same as enabling interrupts and then executing RET
Opcode::RETI => {
self.exec(Opcode::EI, bus);
self.exec(Opcode::RET(OpcodeParameter::NoParam), bus);
},
// WIP
Opcode::HALT => {
self.registers.increment(Register::PC, 1);
},
Opcode::STOP => {
self.registers.increment(Register::PC, 2);
},
Opcode::NOP => self.registers.increment(Register::PC, 1), Opcode::NOP => self.registers.increment(Register::PC, 1),
// _ => println!("Illegal instruction"), // _ => println!("Illegal instruction"),
_ => {}, _ => {},