|
|
b3ba7b309e
|
CP instruction
|
2021-10-17 10:55:16 -05:00 |
|
|
|
b098d28f0e
|
AND, OR and XOR instructions
|
2021-10-16 22:38:13 -05:00 |
|
|
|
12b43ee985
|
Fix PUSH instruction
|
2021-10-16 20:50:31 -05:00 |
|
|
|
989971af8b
|
Implement push and refactor pop
|
2021-10-16 19:41:07 -05:00 |
|
|
|
d24f048c86
|
Another LD instruction
|
2021-10-16 14:50:01 -05:00 |
|
|
|
f94314ad01
|
Fix some bugs and implement a way to compare the logs
|
2021-10-16 14:17:28 -05:00 |
|
|
|
15e3d6685b
|
Fix some bugs on instructions
|
2021-10-16 13:14:02 -05:00 |
|
|
|
afaecf597f
|
Fix some tests, add a couple of new instructions and fix LD instruction bug
|
2021-10-15 20:59:35 -05:00 |
|
|
|
9d8d05c660
|
Including more test roms and initializing the registers
|
2021-10-15 19:49:36 -05:00 |
|
|
|
f9d5cfaa02
|
Refactor 16bit bus read write
|
2021-10-15 19:18:00 -05:00 |
|
|
|
891a72ad73
|
POP and RET instructions
|
2021-10-15 15:08:26 -05:00 |
|
|
|
0a1edfa39e
|
More tests for INC and DEC with 16bit registers
|
2021-10-15 13:44:05 -05:00 |
|
|
|
c55256a5b7
|
Refactor register bit length detection
|
2021-10-15 09:49:35 -05:00 |
|
|
|
dbe95bedf2
|
Increment and decrement instructions
|
2021-10-14 23:58:51 -05:00 |
|
|
|
724cb27c49
|
Functions and tests for detecting half carry
|
2021-10-14 23:32:48 -05:00 |
|
|
|
b2190d1868
|
Refactor enums
|
2021-10-14 21:54:43 -05:00 |
|
|
|
253da76fd5
|
CALL u16 and RST instructions
|
2021-10-14 17:07:51 -05:00 |
|
|
|
d26b77dc78
|
Some refactors
|
2021-10-14 16:13:28 -05:00 |
|
|
|
a5fad87319
|
RLCA, LD and DI instructions
|
2021-10-14 13:25:20 -05:00 |
|
|
|
bc3b25857b
|
Little refactor
|
2021-10-14 08:38:57 -05:00 |
|
|
|
92229e3d93
|
JP u16 instruction
|
2021-10-13 20:50:48 -05:00 |
|
|
|
5d04b7c346
|
Modeling the Bus and writing first test for NOP instruction
|
2021-10-13 19:38:37 -05:00 |
|
|
|
2afa2a1ff8
|
Memory maps
|
2021-10-13 12:56:00 -05:00 |
|
|
|
1902884df9
|
Logic to load a rom file
|
2021-10-12 19:11:52 -05:00 |
|
|
|
1e363187f1
|
Define test for CPU instructions (no tests yet)
|
2021-10-12 18:29:25 -05:00 |
|
|
|
f62926a869
|
Enum most opcode parameters (CB prefix remaining)
|
2021-10-12 18:06:07 -05:00 |
|
|
|
9bf80459a7
|
Add illegal instruction
|
2021-10-12 12:52:04 -05:00 |
|
|
|
bbf6b19957
|
Mapping opcodes
|
2021-10-11 20:38:37 -05:00 |
|
|
|
b6f512f97b
|
Tests for registers getters and setters
|
2021-10-11 13:14:08 -05:00 |
|
|
|
d37699f4a8
|
Functions and tests for some bitwise operations and getter/setter for flag register
|
2021-10-11 12:58:09 -05:00 |
|
|
|
b3e6baaa3f
|
Getters and setters for registers
|
2021-10-11 11:39:13 -05:00 |
|
|
|
9818c57854
|
Define CPU registers
|
2021-10-11 10:53:02 -05:00 |
|
|
|
c6246a9502
|
First commit
|
2021-10-11 09:57:30 -05:00 |
|
