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afaecf597f
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Fix some tests, add a couple of new instructions and fix LD instruction bug
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2021-10-15 20:59:35 -05:00 |
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9d8d05c660
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Including more test roms and initializing the registers
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2021-10-15 19:49:36 -05:00 |
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f9d5cfaa02
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Refactor 16bit bus read write
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2021-10-15 19:18:00 -05:00 |
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891a72ad73
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POP and RET instructions
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2021-10-15 15:08:26 -05:00 |
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0a1edfa39e
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More tests for INC and DEC with 16bit registers
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2021-10-15 13:44:05 -05:00 |
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c55256a5b7
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Refactor register bit length detection
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2021-10-15 09:49:35 -05:00 |
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dbe95bedf2
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Increment and decrement instructions
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2021-10-14 23:58:51 -05:00 |
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724cb27c49
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Functions and tests for detecting half carry
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2021-10-14 23:32:48 -05:00 |
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b2190d1868
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Refactor enums
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2021-10-14 21:54:43 -05:00 |
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253da76fd5
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CALL u16 and RST instructions
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2021-10-14 17:07:51 -05:00 |
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d26b77dc78
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Some refactors
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2021-10-14 16:13:28 -05:00 |
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a5fad87319
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RLCA, LD and DI instructions
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2021-10-14 13:25:20 -05:00 |
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bc3b25857b
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Little refactor
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2021-10-14 08:38:57 -05:00 |
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92229e3d93
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JP u16 instruction
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2021-10-13 20:50:48 -05:00 |
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5d04b7c346
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Modeling the Bus and writing first test for NOP instruction
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2021-10-13 19:38:37 -05:00 |
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1e363187f1
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Define test for CPU instructions (no tests yet)
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2021-10-12 18:29:25 -05:00 |
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f62926a869
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Enum most opcode parameters (CB prefix remaining)
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2021-10-12 18:06:07 -05:00 |
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9bf80459a7
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Add illegal instruction
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2021-10-12 12:52:04 -05:00 |
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bbf6b19957
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Mapping opcodes
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2021-10-11 20:38:37 -05:00 |
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b6f512f97b
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Tests for registers getters and setters
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2021-10-11 13:14:08 -05:00 |
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d37699f4a8
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Functions and tests for some bitwise operations and getter/setter for flag register
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2021-10-11 12:58:09 -05:00 |
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b3e6baaa3f
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Getters and setters for registers
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2021-10-11 11:39:13 -05:00 |
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9818c57854
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Define CPU registers
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2021-10-11 10:53:02 -05:00 |
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