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f928207a8d
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0xF8 instruction
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2021-10-19 11:04:52 -05:00 |
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b6b7e7bf73
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Last interrupt instructions
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2021-10-19 10:41:18 -05:00 |
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ff9fd48190
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SCF instruction
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2021-10-19 10:33:43 -05:00 |
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08513ae110
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CCF Instruction
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2021-10-19 10:30:36 -05:00 |
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ad5211d057
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CPL Instruction
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2021-10-19 10:24:54 -05:00 |
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7bdbfebd0e
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Trim some lines
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2021-10-19 10:12:17 -05:00 |
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9013c09437
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SET instruction
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2021-10-19 10:06:22 -05:00 |
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e4586db39a
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RES instruction
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2021-10-19 10:02:43 -05:00 |
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edc8429aa2
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BIT instruction
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2021-10-19 09:53:50 -05:00 |
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a64d15c9ce
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SWAP instruction
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2021-10-19 09:40:42 -05:00 |
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d1029c1dc7
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Uncommenting some asserts
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2021-10-19 09:26:49 -05:00 |
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3f46ab4a54
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Fix DAA instruction
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2021-10-19 09:22:23 -05:00 |
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f1a035d5ac
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WIP DAA instruction
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2021-10-18 23:24:04 -05:00 |
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b964992f8a
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Implement more JP instructions
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2021-10-18 18:46:17 -05:00 |
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eeeba76ebd
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ADD instruction bug
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2021-10-18 18:18:57 -05:00 |
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ac91f8f50d
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Fix INC and DEC
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2021-10-18 17:27:46 -05:00 |
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199470cc70
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RET instructions
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2021-10-18 16:54:25 -05:00 |
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581e1c19d6
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Bug on RET instruction
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2021-10-18 13:18:15 -05:00 |
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aded5fe534
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ADC and SBC instructions (no tests)
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2021-10-18 13:15:26 -05:00 |
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2b633c9ee0
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RL and RR instructions bug
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2021-10-18 12:45:16 -05:00 |
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ca4a6c9f6a
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Bug RLA and RRA
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2021-10-18 12:31:25 -05:00 |
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59acdd555e
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Fix SRL instruction
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2021-10-18 12:03:24 -05:00 |
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9b08306c96
|
Temporally omitting tests for SLA and SRA
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2021-10-18 10:57:06 -05:00 |
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d093aa483d
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One more test with bus
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2021-10-18 10:33:59 -05:00 |
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aad827f05f
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RR instruction
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2021-10-18 10:25:45 -05:00 |
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8d1a0f6f2f
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RL instruction
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2021-10-18 10:13:23 -05:00 |
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9adf41ee47
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16bit substraction is not really needed
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2021-10-18 08:44:22 -05:00 |
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7c804029ad
|
Some refactors
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2021-10-18 08:28:19 -05:00 |
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f148ee5ba6
|
Prefix CB RRC instruction
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2021-10-17 21:45:55 -05:00 |
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ec34a71fcf
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Mapping CB prefix instructions
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2021-10-17 20:42:36 -05:00 |
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3897c3561e
|
add and sub instructions
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2021-10-17 19:14:41 -05:00 |
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a8f00f46fd
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more CALL instructions
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2021-10-17 13:12:04 -05:00 |
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31e0b2c79c
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Little refactor call instruction
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2021-10-17 12:48:18 -05:00 |
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ebadad803b
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Bug on LD instruction
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2021-10-17 12:29:02 -05:00 |
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b3ba7b309e
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CP instruction
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2021-10-17 10:55:16 -05:00 |
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b098d28f0e
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AND, OR and XOR instructions
|
2021-10-16 22:38:13 -05:00 |
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12b43ee985
|
Fix PUSH instruction
|
2021-10-16 20:50:31 -05:00 |
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989971af8b
|
Implement push and refactor pop
|
2021-10-16 19:41:07 -05:00 |
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d24f048c86
|
Another LD instruction
|
2021-10-16 14:50:01 -05:00 |
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f94314ad01
|
Fix some bugs and implement a way to compare the logs
|
2021-10-16 14:17:28 -05:00 |
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15e3d6685b
|
Fix some bugs on instructions
|
2021-10-16 13:14:02 -05:00 |
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afaecf597f
|
Fix some tests, add a couple of new instructions and fix LD instruction bug
|
2021-10-15 20:59:35 -05:00 |
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9d8d05c660
|
Including more test roms and initializing the registers
|
2021-10-15 19:49:36 -05:00 |
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f9d5cfaa02
|
Refactor 16bit bus read write
|
2021-10-15 19:18:00 -05:00 |
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891a72ad73
|
POP and RET instructions
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2021-10-15 15:08:26 -05:00 |
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0a1edfa39e
|
More tests for INC and DEC with 16bit registers
|
2021-10-15 13:44:05 -05:00 |
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c55256a5b7
|
Refactor register bit length detection
|
2021-10-15 09:49:35 -05:00 |
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dbe95bedf2
|
Increment and decrement instructions
|
2021-10-14 23:58:51 -05:00 |
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724cb27c49
|
Functions and tests for detecting half carry
|
2021-10-14 23:32:48 -05:00 |
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b2190d1868
|
Refactor enums
|
2021-10-14 21:54:43 -05:00 |
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